3051 	chipcregs_t *cc;  in BCMPOSTTRAPFN()
3056 	cc = (chipcregs_t *)si_switch_core(sih, CC_CORE_ID, &origidx, &intr_val);  in BCMPOSTTRAPFN()
4103 	*clk_ctl_st = si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0);  in si_pmu_pll_off()
4125 		if (((si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0)  in si_pmu_pll_off()
4131 		SPINWAIT(((si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0)  in si_pmu_pll_off()
4133 		ASSERT((si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0)  in si_pmu_pll_off()
4145 		SPINWAIT(((si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0)  in si_pmu_pll_off()
4147 		ASSERT(!(si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0)  in si_pmu_pll_off()
4177 	*clk_ctl_st = si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0);  in si_pmu_pll_off_PARR()
4203 		if (((si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0)  in si_pmu_pll_off_PARR()
4210 		SPINWAIT(((si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0)  in si_pmu_pll_off_PARR()
4212 		ASSERT((si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0)  in si_pmu_pll_off_PARR()
4246 		SPINWAIT(((si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0)  in si_pmu_pll_on()
4248 		ASSERT((si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0)  in si_pmu_pll_on()
4682 	chipcregs_t *cc;  in si_mac_clk()
4694 	cc = (chipcregs_t *)si_switch_core(sih, CC_CORE_ID, &origidx, &intr_val);  in si_mac_clk()
4738 	chipcregs_t *cc;  in si_pmu_fvco_macdiv()
4750 	cc = (chipcregs_t *)si_switch_core(sih, CC_CORE_ID, &origidx, &intr_val);  in si_pmu_fvco_macdiv()
4953 		if (si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0)  in BCMATTACHFN()
5191 	si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), CCS_FORCEHT, CCS_FORCEHT)  in BCMATTACHFN()
5975 		otps = si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, otpstatus), 0u, 0u);  in si_pmu_otp_is_ready()
6031 		otpctrl1 = si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, otpcontrol1), 0, 0);  in si_pmu_otp_power()
6036 		si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, otpcontrol1), ~0, otpctrl1);  in si_pmu_otp_power()
7242 	si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), CCS_FORCEALP, CCS_FORCEALP);  in BCMATTACHFN()
8000 			OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0)  in si_pmu_openloop_cal_43012()
8002 		ASSERT((si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0)  in si_pmu_openloop_cal_43012()
8110 	chipcregs_t *cc;  in si_pmu_slow_clk_reinit()
8336 	OFFSETOF(chipcregs_t, clk_ctl_st),
8337 	OFFSETOF(chipcregs_t, powerctl)