Lines Matching refs:W_REG
1722 W_REG(osh, &pmu->min_res_mask, min_mask); in si_pmu_avbtimer_enable()
1723 W_REG(osh, &pmu->max_res_mask, max_mask); in si_pmu_avbtimer_enable()
1953 W_REG(osh, &pmu->res_table_sel, i); in si_pmu_resdeptbl_upd()
1958 W_REG(osh, &pmu->res_dep_mask, in si_pmu_resdeptbl_upd()
2343 W_REG(osh, &pmu->res_table_sel, in BCMATTACHFN()
2345 W_REG(osh, &pmu->res_updn_timer, in BCMATTACHFN()
2370 W_REG(osh, &pmu->res_table_sel, (uint32)i); in BCMATTACHFN()
2371 W_REG(osh, &pmu->res_updn_timer, r_val); in BCMATTACHFN()
2382 W_REG(osh, &pmu->res_table_sel, in BCMATTACHFN()
2386 W_REG(osh, &pmu->rsrc_substate_trans_tmr, in BCMATTACHFN()
2400 W_REG(osh, &pmu->res_table_sel, (uint32)i); in BCMATTACHFN()
2401 W_REG(osh, &pmu->res_dep_mask, (uint32)bcm_strtoul(val, NULL, 0)); in BCMATTACHFN()
2501 W_REG(osh, &pmu->min_res_mask, min_mask); in BCMATTACHFN()
2507 W_REG(osh, &pmu->max_res_mask, max_mask); in BCMATTACHFN()
3628 W_REG(osh, &pmu->pmucontrol, tmp); in BCMATTACHFN()
3782 W_REG(osh, &pmu->pmucontrol, tmp); in BCMATTACHFN()
4391 W_REG(osh, &pmu->clkstretch, CSTRETCH_REDUCE_8); in BCMATTACHFN()
4828 W_REG(osh, &pmu->retention_ctl, ret_ctl); in BCMPOSTTRAPFN()
4859 W_REG(osh, &pmu->pmuintstatus, PMU_INT_STAT_RSRC_EVENT_INT0_MASK); in BCMPOSTTRAPFN()
4892 W_REG(osh, &pmu->min_res_mask, mask); in si_pmu_switch_on_PARLDO()
4894 W_REG(osh, &pmu->max_res_mask, mask); in si_pmu_switch_on_PARLDO()
4924 W_REG(osh, &pmu->min_res_mask, mask); in si_pmu_switch_off_PARLDO()
4926 W_REG(osh, &pmu->max_res_mask, mask); in si_pmu_switch_off_PARLDO()
5124 W_REG(osh, &pmu->slowclkperiod, val); in si_pmu_enb_slow_clk()
5294 W_REG(osh, &pmu->pllcontrol_addr, pll0 + PMU5_PLL_P1P2_OFF); in BCMPOSTTRAPFN()
5300 W_REG(osh, &pmu->pllcontrol_addr, pll0 + PMU5_PLL_M14_OFF); in BCMPOSTTRAPFN()
5305 W_REG(osh, &pmu->pllcontrol_addr, pll0 + PMU5_PLL_NM5_OFF); in BCMPOSTTRAPFN()
5789 W_REG(osh, &pmu->mac_res_req_timer2, PMU32_MAC_SCAN_RSRC_REQ_TIMER); in si_pmu_set_mac_rsrc_req_sc()
5790 W_REG(osh, &pmu->mac_res_req_mask2, deps); in si_pmu_set_mac_rsrc_req_sc()
5873 W_REG(osh, &pmu->mac_res_req_timer, PMU32_MAC_MAIN_RSRC_REQ_TIMER); in si_pmu_set_mac_rsrc_req()
5874 W_REG(osh, &pmu->mac_res_req_mask, si_pmu_rsrc_macphy_clk_deps(sih, osh, macunit)); in si_pmu_set_mac_rsrc_req()
5876 W_REG(osh, &pmu->mac_res_req_timer1, PMU32_MAC_AUX_RSRC_REQ_TIMER); in si_pmu_set_mac_rsrc_req()
5877 W_REG(osh, &pmu->mac_res_req_mask1, si_pmu_rsrc_macphy_clk_deps(sih, osh, macunit)); in si_pmu_set_mac_rsrc_req()
5879 W_REG(osh, &pmu->mac_res_req_timer2, PMU32_MAC_SCAN_RSRC_REQ_TIMER); in si_pmu_set_mac_rsrc_req()
5880 W_REG(osh, &pmu->mac_res_req_mask2, si_pmu_rsrc_macphy_clk_deps(sih, osh, macunit)); in si_pmu_set_mac_rsrc_req()
5907 W_REG(osh, &pmu->res_table_sel, rsrc); in BCMINITFN()
5959 W_REG(osh, &pmu->res_table_sel, i); in si_pmu_res_deps()
6088 W_REG(osh, &pmu->min_res_mask, min_mask); in si_pmu_otp_power()
6113 W_REG(osh, &pmu->min_res_mask, min_mask); in si_pmu_otp_power()
7118 W_REG(osh, &pmu->fis_start_min_res_mask, val); in BCMATTACHFN()
7121 W_REG(osh, &pmu->fis_min_res_mask, val); in BCMATTACHFN()
7123 W_REG(osh, &pmu->fis_ctrl_status, in BCMATTACHFN()
7129 W_REG(osh, &pmu->fis_start_min_res_mask, val); in BCMATTACHFN()
7132 W_REG(osh, &pmu->fis_min_res_mask, val); in BCMATTACHFN()
7134 W_REG(osh, &pmu->fis_ctrl_status, in BCMATTACHFN()
7140 W_REG(osh, &pmu->fis_start_min_res_mask, val); in BCMATTACHFN()
7143 W_REG(osh, &pmu->fis_min_res_mask, val); in BCMATTACHFN()
7145 W_REG(osh, &pmu->fis_ctrl_status, in BCMATTACHFN()
7216 W_REG(osh, &pmu->rsrc_event0, PMURES_BIT(rsrc_slp)); in BCMATTACHFN()
7336 W_REG(osh, &pmu->clkstretch, 0x0fff0fff); in BCMATTACHFN()
7406 W_REG(osh, &pmu->clkstretch, 0x0fff0fff); in BCMATTACHFN()
7597 W_REG(osh, &pmu->min_res_mask, min_mask); in BCMATTACHFN()
7769 W_REG(osh, &pmu->extwakereqmask[0], deps); in BCMATTACHFN()
7792 W_REG(osh, &pmu->min_res_mask, min_mask); in BCMATTACHFN()
8096 W_REG(osh, &pmu->res_table_sel, RES43012_SR_SAVE_RESTORE); in si_pmu_openloop_cal_43012()
8097 W_REG(osh, &pmu->res_updn_timer, 0x01800180); in si_pmu_openloop_cal_43012()
8242 W_REG(osh, &pmu->pmu_xtalfreq, 1U << PMU_XTALFREQ_REG_MEASURE_SHIFT); in BCMATTACHFN()
8251 W_REG(osh, &pmu->pmu_xtalfreq, 0); in BCMATTACHFN()
8314 W_REG(osh, &pmu->min_res_mask, min_mask); in si_pmu_res_minmax_update()
8318 W_REG(osh, &pmu->max_res_mask, max_mask); in si_pmu_res_minmax_update()
8497 W_REG(osh, &pmu->res_table_sel, i); in BCMPOSTTRAPFN()
8884 W_REG(hnd_osh, &pmu->pmuintstatus, in hnd_pmu_clr_int_sts_req_active()
8888 W_REG(hnd_osh, &pmu->res_req_timer, in hnd_pmu_clr_int_sts_req_active()
8909 W_REG(osh, &pmu->min_res_mask, min_res_mask); in si_pmu_set_min_res_mask()
8996 W_REG(osh, &pmu->pllcontrol_addr, PMU1_PLL0_PLLCTL6); in si_pmu_pll6val_armclk_calc()
8997 W_REG(osh, &pmu->pllcontrol_data, pll6val); in si_pmu_pll6val_armclk_calc()
8999 W_REG(osh, &pmu->pllcontrol_addr, PMU1_PLL0_PLLCTL6); in si_pmu_pll6val_armclk_calc()
9251 W_REG(osh, &pmu->pmu_statstimer_addr, timerid); in si_pmustatstimer_update()
9259 W_REG(osh, &pmu->pmu_statstimer_ctrl, stats_timer_ctrl); in si_pmustatstimer_update()
9260 W_REG(osh, &pmu->pmu_statstimer_N, 0); in si_pmustatstimer_update()
9384 W_REG(osh, &pmu->pmu_statstimer_addr, i); in si_pmustatstimer_dump()
9413 W_REG(osh, &pmu->pmu_statstimer_addr, timerid); in si_pmustatstimer_start()
9438 W_REG(osh, &pmu->pmu_statstimer_addr, timerid); in si_pmustatstimer_stop()
9461 W_REG(osh, &pmu->pmu_statstimer_addr, timerid); in si_pmustatstimer_clear()
9462 W_REG(osh, &pmu->pmu_statstimer_N, 0); in si_pmustatstimer_clear()
9492 W_REG(osh, &pmu->pmu_statstimer_addr, i); in si_pmustatstimer_clear_overflow()
9521 W_REG(osh, &pmu->pmu_statstimer_addr, timerid); in si_pmustatstimer_read()
9824 W_REG(osh, &pmu->pmuintmask0, 0); in BCMPOSTTRAPFN()
9830 W_REG(osh, &pmu->pmuintmask1, 0); in BCMPOSTTRAPFN()
9894 W_REG(osh, &pmu->extwakemask0, PMU_EXT_WAKE_MASK_0_PCIE_PERST); in si_pmu_reg_on_war_ext_wake_perst_set()
9900 W_REG(osh, &pmu->extwakereqmask[0], REG_ON_WAR_PMU_EXT_WAKE_REQ_MASK0_VAL); in si_pmu_reg_on_war_ext_wake_perst_set()
9917 W_REG(osh, &pmu->extwakeupstatus, val); in si_pmu_reg_on_war_ext_wake_perst_clear()