290 	pmu_corereg(sih, SI_CC_IDX, pmucontrol,  in si_pmu_pllupd()
568 	pmu_corereg(sih, SI_CC_IDX, regcontrol_addr, /* PMU VREG register */  in si_pmu_set_ldo_voltage()
570 	pmu_corereg(sih, SI_CC_IDX, regcontrol_data,  in si_pmu_set_ldo_voltage()
671 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in BCMINITFN()
1706 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in si_pmu_avbtimer_enable()
1840 				min_mask = pmu_corereg(sih, SI_CC_IDX, min_res_mask, 0, 0);  in si_pmu_res_masks()
1859 				min_mask = pmu_corereg(sih, SI_CC_IDX, min_res_mask, 0, 0);  in si_pmu_res_masks()
1881 				min_mask = pmu_corereg(sih, SI_CC_IDX, min_res_mask, 0, 0);  in si_pmu_res_masks()
2082 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in BCMATTACHFN()
3607 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in BCMATTACHFN()
3808 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in BCMPOSTTRAPFN()
4103 	*clk_ctl_st = si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0);  in si_pmu_pll_off()
4125 		if (((si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0)  in si_pmu_pll_off()
4131 		SPINWAIT(((si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0)  in si_pmu_pll_off()
4133 		ASSERT((si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0)  in si_pmu_pll_off()
4145 		SPINWAIT(((si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0)  in si_pmu_pll_off()
4147 		ASSERT(!(si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0)  in si_pmu_pll_off()
4170 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in si_pmu_pll_off_PARR()
4177 	*clk_ctl_st = si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0);  in si_pmu_pll_off_PARR()
4203 		if (((si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0)  in si_pmu_pll_off_PARR()
4210 		SPINWAIT(((si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0)  in si_pmu_pll_off_PARR()
4212 		ASSERT((si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0)  in si_pmu_pll_off_PARR()
4246 		SPINWAIT(((si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0)  in si_pmu_pll_on()
4248 		ASSERT((si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0)  in si_pmu_pll_on()
4465 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in si_pmu_update_backplane_clock()
4822 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in BCMPOSTTRAPFN()
4851 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in BCMPOSTTRAPFN()
4885 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in si_pmu_switch_on_PARLDO()
4916 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in si_pmu_switch_off_PARLDO()
4953 		if (si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0)  in BCMATTACHFN()
5085 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in si_pmu_enb_slow_clk()
5155 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in BCMATTACHFN()
5191 	si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), CCS_FORCEHT, CCS_FORCEHT)  in BCMATTACHFN()
5218 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in BCMPOSTTRAPFN()
5342 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in BCMPOSTTRAPFN()
5415 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in BCMPOSTTRAPFN()
5526 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in BCMINITFN()
5599 			pmu = si_setcoreidx(sih, SI_CC_IDX);  in BCMINITFN()
5629 	pmu_corereg(sih, SI_CC_IDX, chipcontrol_addr, ~0, reg);  in BCMPOSTTRAPFN()
5630 	return pmu_corereg(sih, SI_CC_IDX, chipcontrol_data, mask, val);  in BCMPOSTTRAPFN()
5641 	pmu_corereg(sih, SI_CC_IDX, regcontrol_addr, ~0, reg);  in BCMPOSTTRAPFN()
5642 	return pmu_corereg(sih, SI_CC_IDX, regcontrol_data, mask, val);  in BCMPOSTTRAPFN()
5653 	pmu_corereg(sih, SI_CC_IDX, pllcontrol_addr, ~0, reg);  in BCMPOSTTRAPFN()
5654 	return pmu_corereg(sih, SI_CC_IDX, pllcontrol_data, mask, val);  in BCMPOSTTRAPFN()
5698 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in BCMATTACHFN()
5716 		pmu_corereg(sih, SI_CC_IDX, pmuintctrl0, val, val);  in BCMATTACHFN()
5719 		pmu_corereg(sih, SI_CC_IDX, pmuintmask0, val, val);  in BCMATTACHFN()
5720 		(void)pmu_corereg(sih, SI_CC_IDX, pmuintmask0, 0, 0);  in BCMATTACHFN()
5741 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in si_pmu_rsrc_macphy_clk_deps()
5809 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in BCMATTACHFN()
5837 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in BCMATTACHFN()
5868 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in si_pmu_set_mac_rsrc_req()
5975 		otps = si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, otpstatus), 0u, 0u);  in si_pmu_otp_is_ready()
6019 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in si_pmu_otp_power()
6031 		otpctrl1 = si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, otpcontrol1), 0, 0);  in si_pmu_otp_power()
6036 		si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, otpcontrol1), ~0, otpctrl1);  in si_pmu_otp_power()
6211 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in si_pmu_is_otp_powered()
6271 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in BCMATTACHFN()
7110 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in BCMATTACHFN()
7189 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in BCMATTACHFN()
7242 	si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), CCS_FORCEALP, CCS_FORCEALP);  in BCMATTACHFN()
7999 		SPINWAIT(((si_corereg(sih, SI_CC_IDX,  in si_pmu_openloop_cal_43012()
8002 		ASSERT((si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0)  in si_pmu_openloop_cal_43012()
8119 	cc = si_setcoreidx(sih, SI_CC_IDX);  in si_pmu_slow_clk_reinit()
8189 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in si_pmu_waitforclk_on_backplane()
8226 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in BCMATTACHFN()
8283 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in si_pmu_res_minmax_update()
8487 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in BCMPOSTTRAPFN()
8608 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in si_pmu_min_res_set()
8881 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in hnd_pmu_clr_int_sts_req_active()
8905 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in si_pmu_set_min_res_mask()
9275 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in si_pmustatstimer_int_enable()
9297 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in si_pmustatstimer_int_disable()
9322 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in si_pmustatstimer_init()
9357 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in si_pmustatstimer_dump()
9407 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in si_pmustatstimer_start()
9432 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in si_pmustatstimer_stop()
9457 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in si_pmustatstimer_clear()
9484 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in si_pmustatstimer_clear_overflow()
9517 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in si_pmustatstimer_read()
9542 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in si_pmustatstimer_cfg_src_num()
9565 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in si_pmustatstimer_cfg_cnt_mode()
9820 		pmu = si_setcoreidx(sih, SI_CC_IDX);  in BCMPOSTTRAPFN()