78 #define PMU_ERROR(args) EVENT_LOG_RA(EVENT_LOG_TAG_PMU_ERROR, args)  macro
80 #define PMU_ERROR(args) EVENT_LOG_COMPACT_CAST_PAREN_ARGS(EVENT_LOG_TAG_PMU_ERROR, args)  macro
83 #define	PMU_ERROR(args)	printf args  macro
85 #define	PMU_ERROR(args)  macro
1908 		PMU_ERROR(("MIN and MAX mask is not programmed\n"));  in si_pmu_res_masks()
2140 				PMU_ERROR(("INVALID: PCIE 1MHz disabled but PMU 1MHz enabled\n"));  in BCMATTACHFN()
3018 		PMU_ERROR(("p1_div calc returned 0! [%d]\n", __LINE__));  in BCMPOSTTRAPFN()
3080 		PMU_ERROR(("pll control register read failed [%d]\n", __LINE__));  in BCMPOSTTRAPFN()
4025 		PMU_ERROR(("si_pmu_pll_delay_43012: PLL not locked!"));  in si_pmu_pll_delay_43012()
4307 			PMU_ERROR(("Default PLL3 value 0x%x is not same as programmed"  in BCMATTACHFN()
4321 		PMU_ERROR(("Failed to get GCI PLL Lock semaphore...\n"));  in BCMATTACHFN()
4357 				PMU_ERROR(("PLL3 programming value 0x%x is not same as programmed"  in BCMATTACHFN()
4409 		PMU_ERROR(("Failed to release GCI PLL Lock semaphore...\n"));  in BCMATTACHFN()
4966 		PMU_ERROR(("si_set_bb_vcofreq_frac: only work on 4360, 4352\n"));  in BCMATTACHFN()
4974 	PMU_ERROR(("ChangeVCO => vco:%d, xtalF:%d, frac: %d, ndivMode: %d, ndivint: %d\n",  in BCMATTACHFN()
4980 	PMU_ERROR(("Data written into the PLL_CNTRL_ADDR2: %08x\n", reg));  in BCMATTACHFN()
4989 		PMU_ERROR(("Data written into the PLL_CNTRL_ADDR3 (Fractional): %08x\n", fraca));  in BCMATTACHFN()
5038 		PMU_ERROR(("si_pmu_get_bb_vcofreq: only work on 4360, 4352, 4369, 4378\n"));  in si_pmu_get_bb_vcofreq()
5059 		PMU_ERROR(("si_pmu_get_bb_vcofreq: xtalfreq is too big, %d\n", xtalfreq));  in si_pmu_get_bb_vcofreq()
5076 		PMU_ERROR(("si_pmu_enb_slow_clk: Not supported %d\n", PMUREV(sih->pmurev)));  in si_pmu_enb_slow_clk()
5115 				PMU_ERROR(("si_pmu_enb_slow_clk: xtalfreq is not supported, %d\n",  in si_pmu_enb_slow_clk()
5284 		PMU_ERROR(("si_pmu5_clock: Bad pll0: %d\n", pll0));  in BCMPOSTTRAPFN()
5290 		PMU_ERROR(("si_pmu5_clock: Bad m divider: %d\n", m));  in BCMPOSTTRAPFN()
5754 		PMU_ERROR(("si_pmu_rsrc_macphy_clk_deps: slice %d is not supported\n", macunit));  in si_pmu_rsrc_macphy_clk_deps()
5986 		PMU_ERROR(("OTP ready bit not %s after wait\n", (on ? "Set" : "Clear")));  in si_pmu_otp_is_ready_and_wait()
6180 		PMU_ERROR(("p1div is invalid\n"));  in si_pmu_pll28nm_fvco()
6303 			PMU_ERROR(("External LPO is not available\n"));  in BCMATTACHFN()
6330 				PMU_ERROR(("External LPO is not set\n"));  in BCMATTACHFN()
6379 				PMU_ERROR(("Internal LPO is not set\n"));  in BCMATTACHFN()
8926 		PMU_ERROR(("si_pmu_fast_lpo_disable: No Fast LPO capability\n"));  in si_pmu_fast_lpo_disable()
8979 		PMU_ERROR((" si_pmu_pll6val_armclk_calc: invalid armclk = %d or xtal = %d\n",  in si_pmu_pll6val_armclk_calc()
9374 	PMU_ERROR(("si_pmustatstimer_dump : TIME %d\n", current_time_ms));  in si_pmustatstimer_dump()
9376 	PMU_ERROR(("\tMAX Timer Num %d, MAX Source Num %d\n",  in si_pmustatstimer_dump()
9378 	PMU_ERROR(("\tpmucapabilities 0x%8x, core_cap_ext 0x%8x, AlpPeriod 0x%8x, ILPPeriod 0x%8x, "  in si_pmustatstimer_dump()
9387 		PMU_ERROR(("\t Timer %d : control 0x%8x, %d\n",  in si_pmustatstimer_dump()
9495 			PMU_ERROR(("pmustatstimer overflow clear - timerid : %d\n", i));  in si_pmustatstimer_clear_overflow()
9800 			PMU_ERROR(("si_pmu_disable_intr_pwrreq: add support for this chip!\n"));  in BCMPOSTTRAPFN()
9854 		PMU_ERROR(("si_pmu_res_state_pwrsw_main_wait: add support for this chip!\n"));  in si_pmu_res_state_pwrsw_main_wait()