Lines Matching refs:PMURES_BIT
851 PMURES_BIT(RES43602_SR_SUBCORE_PWRSW) | PMURES_BIT(RES43602_SR_CLK_STABLE) |
852 PMURES_BIT(RES43602_SR_SAVE_RESTORE) | PMURES_BIT(RES43602_SR_SLEEP) |
853 PMURES_BIT(RES43602_LQ_START) | PMURES_BIT(RES43602_LQ_AVAIL) |
854 PMURES_BIT(RES43602_WL_CORE_RDY) | PMURES_BIT(RES43602_ILP_REQ) |
855 PMURES_BIT(RES43602_ALP_AVAIL) | PMURES_BIT(RES43602_RFLDO_PU) |
856 PMURES_BIT(RES43602_HT_START) | PMURES_BIT(RES43602_HT_AVAIL) |
857 PMURES_BIT(RES43602_MACPHY_CLKAVAIL),
859 PMURES_BIT(RES43602_SERDES_PU),
864 PMURES_BIT(RES43602_SR_CLK_START) | PMURES_BIT(RES43602_SR_PHY_PWRSW) |
865 PMURES_BIT(RES43602_SR_SUBCORE_PWRSW) | PMURES_BIT(RES43602_SR_CLK_STABLE) |
866 PMURES_BIT(RES43602_SR_SAVE_RESTORE) | PMURES_BIT(RES43602_SR_SLEEP) |
867 PMURES_BIT(RES43602_WL_CORE_RDY),
869 PMURES_BIT(RES43602_XTALLDO_PU) | PMURES_BIT(RES43602_XTAL_PU),
874 PMURES_BIT(RES43602_PERST_OVR),
876 PMURES_BIT(RES43602_SR_CLK_START) | PMURES_BIT(RES43602_SR_PHY_PWRSW) |
877 PMURES_BIT(RES43602_SR_SUBCORE_PWRSW) | PMURES_BIT(RES43602_SR_CLK_STABLE) |
878 PMURES_BIT(RES43602_SR_SAVE_RESTORE),
883 PMURES_BIT(RES43602_ALP_AVAIL) | PMURES_BIT(RES43602_RFLDO_PU) |
884 PMURES_BIT(RES43602_HT_START) | PMURES_BIT(RES43602_HT_AVAIL) |
885 PMURES_BIT(RES43602_MACPHY_CLKAVAIL),
887 PMURES_BIT(RES43602_LQ_START) | PMURES_BIT(RES43602_LQ_AVAIL),
897 PMURES_BIT(RES43602_LPLDO_PU) | PMURES_BIT(RES43602_REGULATOR) |
898 PMURES_BIT(RES43602_PMU_SLEEP) | PMURES_BIT(RES43602_RSVD_3) |
899 PMURES_BIT(RES43602_XTALLDO_PU) | PMURES_BIT(RES43602_SERDES_PU) |
900 PMURES_BIT(RES43602_BBPLL_PWRSW_PU) | PMURES_BIT(RES43602_SR_CLK_START) |
901 PMURES_BIT(RES43602_SR_PHY_PWRSW) | PMURES_BIT(RES43602_SR_SUBCORE_PWRSW) |
902 PMURES_BIT(RES43602_XTAL_PU) | PMURES_BIT(RES43602_PERST_OVR) |
903 PMURES_BIT(RES43602_SR_CLK_STABLE) | PMURES_BIT(RES43602_SR_SAVE_RESTORE) |
904 PMURES_BIT(RES43602_SR_SLEEP) | PMURES_BIT(RES43602_LQ_START) |
905 PMURES_BIT(RES43602_LQ_AVAIL) | PMURES_BIT(RES43602_WL_CORE_RDY) |
906 PMURES_BIT(RES43602_ILP_REQ) | PMURES_BIT(RES43602_ALP_AVAIL) |
907 PMURES_BIT(RES43602_RADIO_PU) | PMURES_BIT(RES43602_RFLDO_PU) |
908 PMURES_BIT(RES43602_HT_START) | PMURES_BIT(RES43602_HT_AVAIL) |
909 PMURES_BIT(RES43602_MACPHY_CLKAVAIL) | PMURES_BIT(RES43602_PARLDO_PU) |
910 PMURES_BIT(RES43602_RSVD_26),
913 PMURES_BIT(RES43602_LPLDO_PU),
920 PMURES_BIT(RES43602_PERST_OVR),
922 PMURES_BIT(RES43602_REGULATOR) |
923 PMURES_BIT(RES43602_PMU_SLEEP) |
924 PMURES_BIT(RES43602_XTALLDO_PU) |
925 PMURES_BIT(RES43602_XTAL_PU) |
926 PMURES_BIT(RES43602_RADIO_PU),
930 PMURES_BIT(RES43602_WL_CORE_RDY),
932 PMURES_BIT(RES43602_PERST_OVR),
936 PMURES_BIT(RES43602_LQ_START),
938 PMURES_BIT(RES43602_PERST_OVR),
942 PMURES_BIT(RES43602_LQ_AVAIL),
944 PMURES_BIT(RES43602_PERST_OVR),
948 PMURES_BIT(RES43602_ALP_AVAIL),
950 PMURES_BIT(RES43602_PERST_OVR),
954 PMURES_BIT(RES43602_HT_START),
956 PMURES_BIT(RES43602_PERST_OVR),
960 PMURES_BIT(RES43602_HT_AVAIL),
962 PMURES_BIT(RES43602_PERST_OVR),
966 PMURES_BIT(RES43602_MACPHY_CLKAVAIL),
968 PMURES_BIT(RES43602_PERST_OVR),
980 {PMURES_BIT(RES4369_DUMMY), RES_DEPEND_SET, 0x00000000, NULL},
981 {PMURES_BIT(RES4369_ABUCK), RES_DEPEND_SET, 0x00000005, NULL},
982 {PMURES_BIT(RES4369_PMU_SLEEP), RES_DEPEND_SET, 0x00000001, NULL},
983 {PMURES_BIT(RES4369_MISCLDO), RES_DEPEND_SET, 0x00000007, NULL},
984 {PMURES_BIT(RES4369_LDO3P3), RES_DEPEND_SET, 0x00000001, NULL},
985 {PMURES_BIT(RES4369_FAST_LPO_AVAIL), RES_DEPEND_SET, 0x00000005, NULL},
986 {PMURES_BIT(RES4369_XTAL_PU), RES_DEPEND_SET, 0x00000007, NULL},
987 {PMURES_BIT(RES4369_XTAL_STABLE), RES_DEPEND_SET, 0x00000047, NULL},
988 {PMURES_BIT(RES4369_PWRSW_DIG), RES_DEPEND_SET, 0x060000cf, NULL},
989 {PMURES_BIT(RES4369_SR_DIG), RES_DEPEND_SET, 0x060001cf, NULL},
990 {PMURES_BIT(RES4369_SLEEP_DIG), RES_DEPEND_SET, 0x060003cf, NULL},
991 {PMURES_BIT(RES4369_PWRSW_AUX), RES_DEPEND_SET, 0x040000cf, NULL},
992 {PMURES_BIT(RES4369_SR_AUX), RES_DEPEND_SET, 0x040008cf, NULL},
993 {PMURES_BIT(RES4369_SLEEP_AUX), RES_DEPEND_SET, 0x040018cf, NULL},
994 {PMURES_BIT(RES4369_PWRSW_MAIN), RES_DEPEND_SET, 0x040000cf, NULL},
995 {PMURES_BIT(RES4369_SR_MAIN), RES_DEPEND_SET, 0x040040cf, NULL},
996 {PMURES_BIT(RES4369_SLEEP_MAIN), RES_DEPEND_SET, 0x0400c0cf, NULL},
997 {PMURES_BIT(RES4369_DIG_CORE_RDY), RES_DEPEND_SET, 0x060007cf, NULL},
998 {PMURES_BIT(RES4369_CORE_RDY_AUX), RES_DEPEND_SET, 0x040038cf, NULL},
999 {PMURES_BIT(RES4369_ALP_AVAIL), RES_DEPEND_SET, 0x060207cf, NULL},
1000 {PMURES_BIT(RES4369_RADIO_AUX_PU), RES_DEPEND_SET, 0x040438df, NULL},
1001 {PMURES_BIT(RES4369_MINIPMU_AUX_PU), RES_DEPEND_SET, 0x041438df, NULL},
1002 {PMURES_BIT(RES4369_CORE_RDY_MAIN), RES_DEPEND_SET, 0x0401c0cf, NULL},
1003 {PMURES_BIT(RES4369_RADIO_MAIN_PU), RES_DEPEND_SET, 0x0441c0df, NULL},
1004 {PMURES_BIT(RES4369_MINIPMU_MAIN_PU), RES_DEPEND_SET, 0x04c1c0df, NULL},
1005 {PMURES_BIT(RES4369_PCIE_EP_PU), RES_DEPEND_SET, 0x040000cf, NULL},
1006 {PMURES_BIT(RES4369_COLD_START_WAIT), RES_DEPEND_SET, 0x0000000f, NULL},
1007 {PMURES_BIT(RES4369_ARMHTAVAIL), RES_DEPEND_SET, 0x060a07cf, NULL},
1008 {PMURES_BIT(RES4369_HT_AVAIL), RES_DEPEND_SET, 0x060a07cf, NULL},
1009 {PMURES_BIT(RES4369_MACPHY_AUX_CLK_AVAIL), RES_DEPEND_SET, 0x163e3fdf, NULL},
1010 {PMURES_BIT(RES4369_MACPHY_MAIN_CLK_AVAIL), RES_DEPEND_SET, 0x17cbc7df, NULL},
1014 {PMURES_BIT(RES4369_DUMMY), RES_DEPEND_SET, 0x00000000, NULL},
1015 {PMURES_BIT(RES4369_ABUCK), RES_DEPEND_SET, 0x00000005, NULL},
1016 {PMURES_BIT(RES4369_PMU_SLEEP), RES_DEPEND_SET, 0x00000001, NULL},
1017 {PMURES_BIT(RES4369_MISCLDO), RES_DEPEND_SET, 0x00000007, NULL},
1018 {PMURES_BIT(RES4369_LDO3P3), RES_DEPEND_SET, 0x00000001, NULL},
1019 {PMURES_BIT(RES4369_FAST_LPO_AVAIL), RES_DEPEND_SET, 0x00000005, NULL},
1020 {PMURES_BIT(RES4369_XTAL_PU), RES_DEPEND_SET, 0x00000007, NULL},
1021 {PMURES_BIT(RES4369_XTAL_STABLE), RES_DEPEND_SET, 0x00000047, NULL},
1022 {PMURES_BIT(RES4369_PWRSW_DIG), RES_DEPEND_SET, 0x060000ef, NULL},
1023 {PMURES_BIT(RES4369_SR_DIG), RES_DEPEND_SET, 0x060001ef, NULL},
1024 {PMURES_BIT(RES4369_SLEEP_DIG), RES_DEPEND_SET, 0x060003ef, NULL},
1025 {PMURES_BIT(RES4369_PWRSW_AUX), RES_DEPEND_SET, 0x040000ef, NULL},
1026 {PMURES_BIT(RES4369_SR_AUX), RES_DEPEND_SET, 0x040008ef, NULL},
1027 {PMURES_BIT(RES4369_SLEEP_AUX), RES_DEPEND_SET, 0x040018ef, NULL},
1028 {PMURES_BIT(RES4369_PWRSW_MAIN), RES_DEPEND_SET, 0x040000ef, NULL},
1029 {PMURES_BIT(RES4369_SR_MAIN), RES_DEPEND_SET, 0x040040ef, NULL},
1030 {PMURES_BIT(RES4369_SLEEP_MAIN), RES_DEPEND_SET, 0x0400c0ef, NULL},
1031 {PMURES_BIT(RES4369_DIG_CORE_RDY), RES_DEPEND_SET, 0x060007ef, NULL},
1032 {PMURES_BIT(RES4369_CORE_RDY_AUX), RES_DEPEND_SET, 0x040038ef, NULL},
1033 {PMURES_BIT(RES4369_ALP_AVAIL), RES_DEPEND_SET, 0x060207ef, NULL},
1034 {PMURES_BIT(RES4369_RADIO_AUX_PU), RES_DEPEND_SET, 0x040438ff, NULL},
1035 {PMURES_BIT(RES4369_MINIPMU_AUX_PU), RES_DEPEND_SET, 0x041438ff, NULL},
1036 {PMURES_BIT(RES4369_CORE_RDY_MAIN), RES_DEPEND_SET, 0x0401c0ef, NULL},
1037 {PMURES_BIT(RES4369_RADIO_MAIN_PU), RES_DEPEND_SET, 0x0441c0ff, NULL},
1038 {PMURES_BIT(RES4369_MINIPMU_MAIN_PU), RES_DEPEND_SET, 0x04c1c0ff, NULL},
1039 {PMURES_BIT(RES4369_PCIE_EP_PU), RES_DEPEND_SET, 0x0400002f, NULL},
1040 {PMURES_BIT(RES4369_COLD_START_WAIT), RES_DEPEND_SET, 0x0000002f, NULL},
1041 {PMURES_BIT(RES4369_ARMHTAVAIL), RES_DEPEND_SET, 0x060a07ef, NULL},
1042 {PMURES_BIT(RES4369_HT_AVAIL), RES_DEPEND_SET, 0x060a07ef, NULL},
1043 {PMURES_BIT(RES4369_MACPHY_AUX_CLK_AVAIL), RES_DEPEND_SET, 0x163e3fff, NULL},
1044 {PMURES_BIT(RES4369_MACPHY_MAIN_CLK_AVAIL), RES_DEPEND_SET, 0x17cbc7ff, NULL},
1184 {PMURES_BIT(RES4362_DUMMY), RES_DEPEND_SET, 0x00000000, NULL},
1185 {PMURES_BIT(RES4362_ABUCK), RES_DEPEND_SET, 0x00000005, NULL},
1186 {PMURES_BIT(RES4362_PMU_SLEEP), RES_DEPEND_SET, 0x00000001, NULL},
1187 {PMURES_BIT(RES4362_MISCLDO_PU), RES_DEPEND_SET, 0x00000007, NULL},
1188 {PMURES_BIT(RES4362_LDO3P3_PU), RES_DEPEND_SET, 0x00000005, NULL},
1189 {PMURES_BIT(RES4362_FAST_LPO_AVAIL), RES_DEPEND_SET, 0x00000005, NULL},
1190 {PMURES_BIT(RES4362_XTAL_PU), RES_DEPEND_SET, 0x00000007, NULL},
1191 {PMURES_BIT(RES4362_XTAL_STABLE), RES_DEPEND_SET, 0x00000047, NULL},
1192 {PMURES_BIT(RES4362_PWRSW_DIG), RES_DEPEND_SET, 0x060000cf, NULL},
1193 {PMURES_BIT(RES4362_SR_DIG), RES_DEPEND_SET, 0x060001cf, NULL},
1194 {PMURES_BIT(RES4362_SLEEP_DIG), RES_DEPEND_SET, 0x060003cf, NULL},
1195 {PMURES_BIT(RES4362_PWRSW_AUX), RES_DEPEND_SET, 0x040000cf, NULL},
1196 {PMURES_BIT(RES4362_SR_AUX), RES_DEPEND_SET, 0x040008cf, NULL},
1197 {PMURES_BIT(RES4362_SLEEP_AUX), RES_DEPEND_SET, 0x040018cf, NULL},
1198 {PMURES_BIT(RES4362_PWRSW_MAIN), RES_DEPEND_SET, 0x040000cf, NULL},
1199 {PMURES_BIT(RES4362_SR_MAIN), RES_DEPEND_SET, 0x040040cf, NULL},
1200 {PMURES_BIT(RES4362_SLEEP_MAIN), RES_DEPEND_SET, 0x0400c0cf, NULL},
1201 {PMURES_BIT(RES4362_DIG_CORE_RDY), RES_DEPEND_SET, 0x060007cf, NULL},
1202 {PMURES_BIT(RES4362_CORE_RDY_AUX), RES_DEPEND_SET, 0x040038cf, NULL},
1203 {PMURES_BIT(RES4362_ALP_AVAIL), RES_DEPEND_SET, 0x060207cf, NULL},
1204 {PMURES_BIT(RES4362_RADIO_AUX_PU), RES_DEPEND_SET, 0x040438df, NULL},
1205 {PMURES_BIT(RES4362_MINIPMU_AUX_PU), RES_DEPEND_SET, 0x041438df, NULL},
1206 {PMURES_BIT(RES4362_CORE_RDY_MAIN), RES_DEPEND_SET, 0x0401c0cf, NULL},
1207 {PMURES_BIT(RES4362_RADIO_MAIN_PU), RES_DEPEND_SET, 0x0441c0df, NULL},
1208 {PMURES_BIT(RES4362_MINIPMU_MAIN_PU), RES_DEPEND_SET, 0x04c1c0df, NULL},
1209 {PMURES_BIT(RES4362_PCIE_EP_PU), RES_DEPEND_SET, 0x040000cf, NULL},
1210 {PMURES_BIT(RES4362_COLD_START_WAIT), RES_DEPEND_SET, 0x0000000f, NULL},
1211 {PMURES_BIT(RES4362_ARMHTAVAIL), RES_DEPEND_SET, 0x060a07cf, NULL},
1212 {PMURES_BIT(RES4362_HT_AVAIL), RES_DEPEND_SET, 0x060a07cf, NULL},
1213 {PMURES_BIT(RES4362_MACPHY_AUX_CLK_AVAIL), RES_DEPEND_SET, 0x163e3fdf, NULL},
1214 {PMURES_BIT(RES4362_MACPHY_MAIN_CLK_AVAIL), RES_DEPEND_SET, 0x17cbc7df, NULL},
1272 {PMURES_BIT(RES4378_ABUCK), RES_DEPEND_SET, 0x00000005, NULL},
1273 {PMURES_BIT(RES4378_PMU_SLEEP), RES_DEPEND_SET, 0x00000001, NULL},
1274 {PMURES_BIT(RES4378_MISC_LDO), RES_DEPEND_SET, 0x00000007, NULL},
1275 {PMURES_BIT(RES4378_LDO3P3_PU), RES_DEPEND_SET, 0x00000001, NULL},
1276 {PMURES_BIT(RES4378_FAST_LPO_AVAIL), RES_DEPEND_SET, 0x00000005, NULL},
1277 {PMURES_BIT(RES4378_XTAL_PU), RES_DEPEND_SET, 0x00000007, NULL},
1278 {PMURES_BIT(RES4378_XTAL_STABLE), RES_DEPEND_SET, 0x00000047, NULL},
1279 {PMURES_BIT(RES4378_PWRSW_DIG), RES_DEPEND_SET, 0x060000ef, NULL},
1280 {PMURES_BIT(RES4378_SR_DIG), RES_DEPEND_SET, 0x060001ef, NULL},
1281 {PMURES_BIT(RES4378_SLEEP_DIG), RES_DEPEND_SET, 0x060003ef, NULL},
1282 {PMURES_BIT(RES4378_PWRSW_AUX), RES_DEPEND_SET, 0x060000ef, NULL},
1283 {PMURES_BIT(RES4378_SR_AUX), RES_DEPEND_SET, 0x060008ef, NULL},
1284 {PMURES_BIT(RES4378_SLEEP_AUX), RES_DEPEND_SET, 0x060018ef, NULL},
1285 {PMURES_BIT(RES4378_PWRSW_MAIN), RES_DEPEND_SET, 0x060000ef, NULL},
1286 {PMURES_BIT(RES4378_SR_MAIN), RES_DEPEND_SET, 0x060040ef, NULL},
1287 {PMURES_BIT(RES4378_SLEEP_MAIN), RES_DEPEND_SET, 0x0600c0ef, NULL},
1288 {PMURES_BIT(RES4378_CORE_RDY_DIG), RES_DEPEND_SET, 0x060007ef, NULL},
1289 {PMURES_BIT(RES4378_CORE_RDY_AUX), RES_DEPEND_SET, 0x06023fef, NULL},
1290 {PMURES_BIT(RES4378_ALP_AVAIL), RES_DEPEND_SET, 0x000000c7, NULL},
1291 {PMURES_BIT(RES4378_RADIO_AUX_PU), RES_DEPEND_SET, 0x06063fff, NULL},
1292 {PMURES_BIT(RES4378_MINIPMU_AUX_PU), RES_DEPEND_SET, 0x06163fff, NULL},
1293 {PMURES_BIT(RES4378_CORE_RDY_MAIN), RES_DEPEND_SET, 0x0603c7ef, NULL},
1294 {PMURES_BIT(RES4378_RADIO_MAIN_PU), RES_DEPEND_SET, 0x0643c7ff, NULL},
1295 {PMURES_BIT(RES4378_MINIPMU_MAIN_PU), RES_DEPEND_SET, 0x06c3c7ff, NULL},
1297 {PMURES_BIT(RES4378_CORE_RDY_CB), RES_DEPEND_SET, 0x0400002f, NULL},
1299 {PMURES_BIT(RES4378_CORE_RDY_CB), RES_DEPEND_SET, 0x040000ef, NULL},
1301 {PMURES_BIT(RES4378_PWRSW_CB), RES_DEPEND_SET, 0x0000002f, NULL},
1302 {PMURES_BIT(RES4378_ARMHTAVAIL), RES_DEPEND_SET, 0x000800c7, NULL},
1303 {PMURES_BIT(RES4378_HT_AVAIL), RES_DEPEND_SET, 0x000800c7, NULL},
1304 {PMURES_BIT(RES4378_MACPHY_AUX_CLK_AVAIL), RES_DEPEND_SET, 0x163e3fff, NULL},
1305 {PMURES_BIT(RES4378_MACPHY_MAIN_CLK_AVAIL), RES_DEPEND_SET, 0x17cbc7ff, NULL},
1367 {PMURES_BIT(RES4387_DUMMY), RES_DEPEND_SET, 0x0, NULL},
1368 {PMURES_BIT(RES4387_RESERVED_1), RES_DEPEND_SET, 0x0, NULL},
1369 {PMURES_BIT(RES4387_PMU_SLEEP), RES_DEPEND_SET, 0x1, NULL},
1370 {PMURES_BIT(RES4387_MISC_LDO), RES_DEPEND_SET, 0x5, NULL},
1371 {PMURES_BIT(RES4387_RESERVED_4), RES_DEPEND_SET, 0x0, NULL},
1372 {PMURES_BIT(RES4387_XTAL_HQ), RES_DEPEND_SET, 0xc5, NULL},
1373 {PMURES_BIT(RES4387_XTAL_PU), RES_DEPEND_SET, 0x5, NULL},
1374 {PMURES_BIT(RES4387_XTAL_STABLE), RES_DEPEND_SET, 0x45, NULL},
1375 {PMURES_BIT(RES4387_PWRSW_DIG), RES_DEPEND_SET, 0x060000CD, NULL},
1376 {PMURES_BIT(RES4387_CORE_RDY_BTMAIN), RES_DEPEND_SET, 0xCD, NULL},
1377 {PMURES_BIT(RES4387_CORE_RDY_BTSC), RES_DEPEND_SET, 0xC5, NULL},
1378 {PMURES_BIT(RES4387_PWRSW_AUX), RES_DEPEND_SET, 0xCD, NULL},
1379 {PMURES_BIT(RES4387_PWRSW_SCAN), RES_DEPEND_SET, 0xCD, NULL},
1380 {PMURES_BIT(RES4387_CORE_RDY_SCAN), RES_DEPEND_SET, 0x060010CD, NULL},
1381 {PMURES_BIT(RES4387_PWRSW_MAIN), RES_DEPEND_SET, 0xCD, NULL},
1382 {PMURES_BIT(RES4387_RESERVED_15), RES_DEPEND_SET, 0x0, NULL},
1383 {PMURES_BIT(RES4387_RESERVED_16), RES_DEPEND_SET, 0x0, NULL},
1384 {PMURES_BIT(RES4387_CORE_RDY_DIG), RES_DEPEND_SET, 0x060001CD, NULL},
1385 {PMURES_BIT(RES4387_CORE_RDY_AUX), RES_DEPEND_SET, 0x060209CD, NULL},
1386 {PMURES_BIT(RES4387_ALP_AVAIL), RES_DEPEND_SET, 0xC5, NULL},
1387 {PMURES_BIT(RES4387_RADIO_PU_AUX), RES_DEPEND_SET, 0x060609CD, NULL},
1388 {PMURES_BIT(RES4387_RADIO_PU_SCAN), RES_DEPEND_SET, 0x060030CD, NULL},
1389 {PMURES_BIT(RES4387_CORE_RDY_MAIN), RES_DEPEND_SET, 0x060241CD, NULL},
1390 {PMURES_BIT(RES4387_RADIO_PU_MAIN), RES_DEPEND_SET, 0x064241CD, NULL},
1391 {PMURES_BIT(RES4387_MACPHY_CLK_SCAN), RES_DEPEND_SET, 0x162830CD, NULL},
1392 {PMURES_BIT(RES4387_CORE_RDY_CB), RES_DEPEND_SET, 0x0400000D, NULL},
1393 {PMURES_BIT(RES4387_PWRSW_CB), RES_DEPEND_SET, 0x0000000D, NULL},
1394 {PMURES_BIT(RES4387_ARMCLK_AVAIL), RES_DEPEND_SET, 0x000800CD, NULL},
1395 {PMURES_BIT(RES4387_HT_AVAIL), RES_DEPEND_SET, 0x000800CD, NULL},
1396 {PMURES_BIT(RES4387_MACPHY_CLK_AUX), RES_DEPEND_SET, 0x161E09ED, NULL},
1397 {PMURES_BIT(RES4387_MACPHY_CLK_MAIN), RES_DEPEND_SET, 0x16CA41ED, NULL},
1453 {PMURES_BIT(RES4387_DUMMY), RES_DEPEND_SET, 0x0, NULL},
1454 {PMURES_BIT(RES4387_FAST_LPO_AVAIL), RES_DEPEND_SET, 0x0, NULL},
1455 {PMURES_BIT(RES4387_PMU_LP), RES_DEPEND_SET, 0x1, NULL},
1456 {PMURES_BIT(RES4387_MISC_LDO), RES_DEPEND_SET, 0x5, NULL},
1457 {PMURES_BIT(RES4387_SERDES_AFE_RET), RES_DEPEND_SET, 0xD, NULL},
1458 {PMURES_BIT(RES4387_XTAL_HQ), RES_DEPEND_SET, 0xC5, NULL},
1459 {PMURES_BIT(RES4387_XTAL_PU), RES_DEPEND_SET, 0x5, NULL},
1460 {PMURES_BIT(RES4387_XTAL_STABLE), RES_DEPEND_SET, 0x45, NULL},
1461 {PMURES_BIT(RES4387_PWRSW_DIG), RES_DEPEND_SET, 0x060000DD, NULL},
1462 {PMURES_BIT(RES4387_CORE_RDY_BTMAIN), RES_DEPEND_SET, 0xCD, NULL},
1463 {PMURES_BIT(RES4387_CORE_RDY_BTSC), RES_DEPEND_SET, 0xC5, NULL},
1464 {PMURES_BIT(RES4387_PWRSW_AUX), RES_DEPEND_SET, 0xCD, NULL},
1465 {PMURES_BIT(RES4387_PWRSW_SCAN), RES_DEPEND_SET, 0xCD, NULL},
1466 {PMURES_BIT(RES4387_CORE_RDY_SCAN), RES_DEPEND_SET, 0x060010DD, NULL},
1467 {PMURES_BIT(RES4387_PWRSW_MAIN), RES_DEPEND_SET, 0xCD, NULL},
1468 {PMURES_BIT(RES4387_XTAL_PM_CLK), RES_DEPEND_SET, 0xC5, NULL},
1469 {PMURES_BIT(RES4387_RESERVED_16), RES_DEPEND_SET, 0x0, NULL},
1470 {PMURES_BIT(RES4387_CORE_RDY_DIG), RES_DEPEND_SET, 0x060001DD, NULL},
1471 {PMURES_BIT(RES4387_CORE_RDY_AUX), RES_DEPEND_SET, 0x060209DD, NULL},
1472 {PMURES_BIT(RES4387_ALP_AVAIL), RES_DEPEND_SET, 0x80C5, NULL},
1473 {PMURES_BIT(RES4387_RADIO_PU_AUX), RES_DEPEND_SET, 0x060609DD, NULL},
1474 {PMURES_BIT(RES4387_RADIO_PU_SCAN), RES_DEPEND_SET, 0x060030DD, NULL},
1475 {PMURES_BIT(RES4387_CORE_RDY_MAIN), RES_DEPEND_SET, 0x060241DD, NULL},
1476 {PMURES_BIT(RES4387_RADIO_PU_MAIN), RES_DEPEND_SET, 0x064241DD, NULL},
1477 {PMURES_BIT(RES4387_MACPHY_CLK_SCAN), RES_DEPEND_SET, 0x1628B0DD, NULL},
1478 {PMURES_BIT(RES4387_CORE_RDY_CB), RES_DEPEND_SET, 0x0400001D, NULL},
1479 {PMURES_BIT(RES4387_PWRSW_CB), RES_DEPEND_SET, 0x0000001D, NULL},
1480 {PMURES_BIT(RES4387_ARMCLK_AVAIL), RES_DEPEND_SET, 0x000880CD, NULL},
1481 {PMURES_BIT(RES4387_HT_AVAIL), RES_DEPEND_SET, 0x000880CD, NULL},
1482 {PMURES_BIT(RES4387_MACPHY_CLK_AUX), RES_DEPEND_SET, 0x161E89FD, NULL},
1483 {PMURES_BIT(RES4387_MACPHY_CLK_MAIN), RES_DEPEND_SET, 0x16CAC1FD, NULL},
1557 {PMURES_BIT(RES4388_DUMMY), RES_DEPEND_SET, 0x00000000, NULL},
1558 {PMURES_BIT(RES4388_FAST_LPO_AVAIL), RES_DEPEND_SET, 0x00000000, NULL},
1559 {PMURES_BIT(RES4388_PMU_LP), RES_DEPEND_SET, 0x00000001, NULL},
1560 {PMURES_BIT(RES4388_MISC_LDO), RES_DEPEND_SET, 0x00000005, NULL},
1561 {PMURES_BIT(RES4388_SERDES_AFE_RET), RES_DEPEND_SET, 0x0000000d, NULL},
1562 {PMURES_BIT(RES4388_XTAL_HQ), RES_DEPEND_SET, 0x000000c5, NULL},
1563 {PMURES_BIT(RES4388_XTAL_PU), RES_DEPEND_SET, 0x00000005, NULL},
1564 {PMURES_BIT(RES4388_XTAL_STABLE), RES_DEPEND_SET, 0x00000045, NULL},
1565 {PMURES_BIT(RES4388_PWRSW_DIG), RES_DEPEND_SET, 0x060000dd, NULL},
1566 {PMURES_BIT(RES4388_BTMC_TOP_RDY), RES_DEPEND_SET, 0x000000cd, NULL},
1567 {PMURES_BIT(RES4388_BTSC_TOP_RDY), RES_DEPEND_SET, 0x000000c5, NULL},
1568 {PMURES_BIT(RES4388_PWRSW_AUX), RES_DEPEND_SET, 0x000000cd, NULL},
1569 {PMURES_BIT(RES4388_PWRSW_SCAN), RES_DEPEND_SET, 0x000000cd, NULL},
1570 {PMURES_BIT(RES4388_CORE_RDY_SCAN), RES_DEPEND_SET, 0x060211dd, NULL},
1571 {PMURES_BIT(RES4388_PWRSW_MAIN), RES_DEPEND_SET, 0x000000cd, NULL},
1572 {PMURES_BIT(RES4388_RESERVED_15), RES_DEPEND_SET, 0x00000000, NULL},
1573 {PMURES_BIT(RES4388_RESERVED_16), RES_DEPEND_SET, 0x00000000, NULL},
1574 {PMURES_BIT(RES4388_CORE_RDY_DIG), RES_DEPEND_SET, 0x060001dd, NULL},
1575 {PMURES_BIT(RES4388_CORE_RDY_AUX), RES_DEPEND_SET, 0x060209dd, NULL},
1576 {PMURES_BIT(RES4388_ALP_AVAIL), RES_DEPEND_SET, 0x000000c5, NULL},
1577 {PMURES_BIT(RES4388_RADIO_PU_AUX), RES_DEPEND_SET, 0x060609dd, NULL},
1578 {PMURES_BIT(RES4388_RADIO_PU_SCAN), RES_DEPEND_SET, 0x060231dd, NULL},
1579 {PMURES_BIT(RES4388_CORE_RDY_MAIN), RES_DEPEND_SET, 0x060241dd, NULL},
1580 {PMURES_BIT(RES4388_RADIO_PU_MAIN), RES_DEPEND_SET, 0x064241dd, NULL},
1581 {PMURES_BIT(RES4388_MACPHY_CLK_SCAN), RES_DEPEND_SET, 0x162a31fd, NULL},
1582 {PMURES_BIT(RES4388_CORE_RDY_CB), RES_DEPEND_SET, 0x040000dd, NULL},
1583 {PMURES_BIT(RES4388_PWRSW_CB), RES_DEPEND_SET, 0x000000dd, NULL},
1584 {PMURES_BIT(RES4388_ARMCLKAVAIL), RES_DEPEND_SET, 0x000800cd, NULL},
1585 {PMURES_BIT(RES4388_HT_AVAIL), RES_DEPEND_SET, 0x000800cd, NULL},
1586 {PMURES_BIT(RES4388_MACPHY_CLK_AUX), RES_DEPEND_SET, 0x161e09fd, NULL},
1587 {PMURES_BIT(RES4388_MACPHY_CLK_MAIN), RES_DEPEND_SET, 0x16ca41fd, NULL},
1661 {PMURES_BIT(RES4389_DUMMY), RES_DEPEND_SET, 0x00000000, NULL},
1662 {PMURES_BIT(RES4389_FAST_LPO_AVAIL), RES_DEPEND_SET, 0x00000000, NULL},
1663 {PMURES_BIT(RES4389_PMU_LP), RES_DEPEND_SET, 0x00000001, NULL},
1664 {PMURES_BIT(RES4389_MISC_LDO), RES_DEPEND_SET, 0x00000005, NULL},
1665 {PMURES_BIT(RES4389_SERDES_AFE_RET), RES_DEPEND_SET, 0x0000000d, NULL},
1666 {PMURES_BIT(RES4389_XTAL_HQ), RES_DEPEND_SET, 0x000000c5, NULL},
1667 {PMURES_BIT(RES4389_XTAL_PU), RES_DEPEND_SET, 0x00000005, NULL},
1668 {PMURES_BIT(RES4389_XTAL_STABLE), RES_DEPEND_SET, 0x00000045, NULL},
1669 {PMURES_BIT(RES4389_PWRSW_DIG), RES_DEPEND_SET, 0x060000dd, NULL},
1670 {PMURES_BIT(RES4389_BTMC_TOP_RDY), RES_DEPEND_SET, 0x000000cd, NULL},
1671 {PMURES_BIT(RES4389_BTSC_TOP_RDY), RES_DEPEND_SET, 0x000000c5, NULL},
1672 {PMURES_BIT(RES4389_PWRSW_AUX), RES_DEPEND_SET, 0x000000cd, NULL},
1673 {PMURES_BIT(RES4389_PWRSW_SCAN), RES_DEPEND_SET, 0x000000cd, NULL},
1674 {PMURES_BIT(RES4389_CORE_RDY_SCAN), RES_DEPEND_SET, 0x060211dd, NULL},
1675 {PMURES_BIT(RES4389_PWRSW_MAIN), RES_DEPEND_SET, 0x000000cd, NULL},
1676 {PMURES_BIT(RES4389_RESERVED_15), RES_DEPEND_SET, 0x00000000, NULL},
1677 {PMURES_BIT(RES4389_RESERVED_16), RES_DEPEND_SET, 0x00000000, NULL},
1678 {PMURES_BIT(RES4389_CORE_RDY_DIG), RES_DEPEND_SET, 0x060001dd, NULL},
1679 {PMURES_BIT(RES4389_CORE_RDY_AUX), RES_DEPEND_SET, 0x060209dd, NULL},
1680 {PMURES_BIT(RES4389_ALP_AVAIL), RES_DEPEND_SET, 0x000000c5, NULL},
1681 {PMURES_BIT(RES4389_RADIO_PU_AUX), RES_DEPEND_SET, 0x060609dd, NULL},
1682 {PMURES_BIT(RES4389_RADIO_PU_SCAN), RES_DEPEND_SET, 0x060231dd, NULL},
1683 {PMURES_BIT(RES4389_CORE_RDY_MAIN), RES_DEPEND_SET, 0x060241dd, NULL},
1684 {PMURES_BIT(RES4389_RADIO_PU_MAIN), RES_DEPEND_SET, 0x064241dd, NULL},
1685 {PMURES_BIT(RES4389_MACPHY_CLK_SCAN), RES_DEPEND_SET, 0x162a31fd, NULL},
1686 {PMURES_BIT(RES4389_CORE_RDY_CB), RES_DEPEND_SET, 0x040000dd, NULL},
1687 {PMURES_BIT(RES4389_PWRSW_CB), RES_DEPEND_SET, 0x000000dd, NULL},
1688 {PMURES_BIT(RES4389_ARMCLKAVAIL), RES_DEPEND_SET, 0x000800cd, NULL},
1689 {PMURES_BIT(RES4389_HT_AVAIL), RES_DEPEND_SET, 0x000800cd, NULL},
1690 {PMURES_BIT(RES4389_MACPHY_CLK_AUX), RES_DEPEND_SET, 0x161e09fd, NULL},
1691 {PMURES_BIT(RES4389_MACPHY_CLK_MAIN), RES_DEPEND_SET, 0x16ca41fd, NULL},
1718 max_mask |= PMURES_BIT(RES4360_AVB_PLL_PWRSW_PU); in si_pmu_avbtimer_enable()
1719 max_mask |= PMURES_BIT(RES4360_PCIE_TL_CLK_AVAIL); in si_pmu_avbtimer_enable()
1720 min_mask |= PMURES_BIT(RES4360_AVB_PLL_PWRSW_PU); in si_pmu_avbtimer_enable()
1721 min_mask |= PMURES_BIT(RES4360_PCIE_TL_CLK_AVAIL); in si_pmu_avbtimer_enable()
1726 ~PMURES_BIT(RES4360_AVB_PLL_PWRSW_PU)); in si_pmu_avbtimer_enable()
1728 ~PMURES_BIT(RES4360_PCIE_TL_CLK_AVAIL)); in si_pmu_avbtimer_enable()
1730 ~PMURES_BIT(RES4360_AVB_PLL_PWRSW_PU)); in si_pmu_avbtimer_enable()
1732 ~PMURES_BIT(RES4360_PCIE_TL_CLK_AVAIL)); in si_pmu_avbtimer_enable()
1772 min_mask = PMURES_BIT(RES43602_LPLDO_PU) | PMURES_BIT(RES43602_REGULATOR) | in si_pmu_res_masks()
1773 PMURES_BIT(RES43602_PMU_SLEEP) | PMURES_BIT(RES43602_XTALLDO_PU) | in si_pmu_res_masks()
1774 PMURES_BIT(RES43602_SERDES_PU) | PMURES_BIT(RES43602_BBPLL_PWRSW_PU) | in si_pmu_res_masks()
1775 PMURES_BIT(RES43602_SR_CLK_START) | PMURES_BIT(RES43602_SR_PHY_PWRSW) | in si_pmu_res_masks()
1776 PMURES_BIT(RES43602_SR_SUBCORE_PWRSW) | PMURES_BIT(RES43602_XTAL_PU) | in si_pmu_res_masks()
1777 PMURES_BIT(RES43602_PERST_OVR) | PMURES_BIT(RES43602_SR_CLK_STABLE) | in si_pmu_res_masks()
1778 PMURES_BIT(RES43602_SR_SAVE_RESTORE) | PMURES_BIT(RES43602_SR_SLEEP) | in si_pmu_res_masks()
1779 PMURES_BIT(RES43602_LQ_START) | PMURES_BIT(RES43602_LQ_AVAIL) | in si_pmu_res_masks()
1780 PMURES_BIT(RES43602_WL_CORE_RDY) | in si_pmu_res_masks()
1781 PMURES_BIT(RES43602_ALP_AVAIL); in si_pmu_res_masks()
1784 min_mask &= ~PMURES_BIT(RES43602_LPLDO_PU); in si_pmu_res_masks()
1786 max_mask = (1<<3) | min_mask | PMURES_BIT(RES43602_RADIO_PU) | in si_pmu_res_masks()
1787 PMURES_BIT(RES43602_RFLDO_PU) | PMURES_BIT(RES43602_HT_START) | in si_pmu_res_masks()
1788 PMURES_BIT(RES43602_HT_AVAIL) | PMURES_BIT(RES43602_MACPHY_CLKAVAIL); in si_pmu_res_masks()
1794 min_mask = PMURES_BIT(RES43602_LPLDO_PU); in si_pmu_res_masks()
1826 min_mask = PMURES_BIT(RES4378_DUMMY); in si_pmu_res_masks()
1838 min_mask = PMURES_BIT(RES4387_DUMMY); in si_pmu_res_masks()
1842 min_mask |= PMURES_BIT(RES4387_FAST_LPO_AVAIL) | in si_pmu_res_masks()
1843 PMURES_BIT(RES4387_PMU_LP); in si_pmu_res_masks()
1857 min_mask = PMURES_BIT(RES4388_DUMMY); in si_pmu_res_masks()
1861 min_mask |= PMURES_BIT(RES4388_FAST_LPO_AVAIL) | in si_pmu_res_masks()
1862 PMURES_BIT(RES4388_PMU_LP); in si_pmu_res_masks()
1879 min_mask = PMURES_BIT(RES4389_DUMMY); in si_pmu_res_masks()
1883 min_mask |= PMURES_BIT(RES4389_FAST_LPO_AVAIL) | in si_pmu_res_masks()
1884 PMURES_BIT(RES4389_PMU_LP); in si_pmu_res_masks()
1901 min_mask = (PMURES_BIT(RES4362_DUMMY)); in si_pmu_res_masks()
1951 PMURES_BIT(i)) == 0) in si_pmu_resdeptbl_upd()
1995 PMURES_BIT(RES4387_FAST_LPO_AVAIL)) { in BCMATTACHFN()
1996 pmu_res_depend_table[i].depend_mask = PMURES_BIT(RES4387_DUMMY) | in BCMATTACHFN()
1997 PMURES_BIT(RES4387_PMU_LP); in BCMATTACHFN()
1999 PMURES_BIT(RES4387_DUMMY)) && in BCMATTACHFN()
2001 PMURES_BIT(RES4387_PMU_LP)) && in BCMATTACHFN()
2003 PMURES_BIT(RES4387_RESERVED_16))) { in BCMATTACHFN()
2005 PMURES_BIT(RES4387_FAST_LPO_AVAIL); in BCMATTACHFN()
2012 PMURES_BIT(RES4388_FAST_LPO_AVAIL)) { in BCMATTACHFN()
2013 pmu_res_depend_table[i].depend_mask = PMURES_BIT(RES4388_DUMMY) | in BCMATTACHFN()
2014 PMURES_BIT(RES4388_PMU_LP); in BCMATTACHFN()
2016 PMURES_BIT(RES4388_DUMMY)) && in BCMATTACHFN()
2018 PMURES_BIT(RES4388_PMU_LP)) && in BCMATTACHFN()
2020 PMURES_BIT(RES4388_RESERVED_15)) && in BCMATTACHFN()
2022 PMURES_BIT(RES4388_RESERVED_16))) { in BCMATTACHFN()
2024 PMURES_BIT(RES4388_FAST_LPO_AVAIL); in BCMATTACHFN()
2031 PMURES_BIT(RES4389_FAST_LPO_AVAIL)) { in BCMATTACHFN()
2032 pmu_res_depend_table[i].depend_mask = PMURES_BIT(RES4389_DUMMY) | in BCMATTACHFN()
2033 PMURES_BIT(RES4389_PMU_LP); in BCMATTACHFN()
2035 PMURES_BIT(RES4389_DUMMY)) && in BCMATTACHFN()
2037 PMURES_BIT(RES4389_PMU_LP)) && in BCMATTACHFN()
2039 PMURES_BIT(RES4389_RESERVED_16))) { in BCMATTACHFN()
2041 PMURES_BIT(RES4389_FAST_LPO_AVAIL); in BCMATTACHFN()
3240 uint32 ht_req = (PMURES_BIT(rsc->ht_avail) | PMURES_BIT(rsc->macphy_clkavail)); in si_pmu_htclk_mask()
3257 ht_req |= PMURES_BIT(rsc->ht_start); in si_pmu_htclk_mask()
4891 mask = R_REG(osh, &pmu->min_res_mask) | PMURES_BIT(RES43602_PARLDO_PU); in si_pmu_switch_on_PARLDO()
4893 mask = R_REG(osh, &pmu->max_res_mask) | PMURES_BIT(RES43602_PARLDO_PU); in si_pmu_switch_on_PARLDO()
4923 mask = R_REG(osh, &pmu->min_res_mask) & ~PMURES_BIT(RES43602_PARLDO_PU); in si_pmu_switch_off_PARLDO()
4925 mask = R_REG(osh, &pmu->max_res_mask) & ~PMURES_BIT(RES43602_PARLDO_PU); in si_pmu_switch_off_PARLDO()
5758 deps = si_pmu_res_deps(sih, osh, pmu, PMURES_BIT(rsc_num), TRUE); in si_pmu_rsrc_macphy_clk_deps()
5759 deps |= PMURES_BIT(rsc_num); in si_pmu_rsrc_macphy_clk_deps()
5783 rsrc = (PMURES_BIT(rsc->macphy_scan_clkavail) | in si_pmu_set_mac_rsrc_req_sc()
5784 PMURES_BIT(rsc->dig_ready)); in si_pmu_set_mac_rsrc_req_sc()
5815 deps = si_pmu_res_deps(sih, osh, pmu, PMURES_BIT(rsc->ht_avail), FALSE); in BCMATTACHFN()
5816 deps |= PMURES_BIT(rsc->ht_avail); in BCMATTACHFN()
5846 deps = si_pmu_res_deps(sih, osh, pmu, PMURES_BIT(rsc->cb_ready), FALSE); in BCMATTACHFN()
5847 deps |= PMURES_BIT(rsc->cb_ready); in BCMATTACHFN()
5916 deps = si_pmu_res_deps(sih, osh, pmu, PMURES_BIT(rsrc), FALSE); in BCMINITFN()
5918 if (!(deps & PMURES_BIT(i))) in BCMINITFN()
5920 deps &= ~si_pmu_res_deps(sih, osh, pmu, PMURES_BIT(i), TRUE); in BCMINITFN()
5933 if (!(deps & PMURES_BIT(i))) in BCMINITFN()
5957 if (!(rsrcs & PMURES_BIT(i))) in si_pmu_res_deps()
6057 rsrcs = PMURES_BIT(rsc->otp_pu); in si_pmu_otp_power()
6230 st = (R_REG(osh, &pmu->res_state) & PMURES_BIT(rsc->otp_pu)) != 0; in si_pmu_is_otp_powered()
7216 W_REG(osh, &pmu->rsrc_event0, PMURES_BIT(rsrc_slp)); in BCMATTACHFN()
7595 PMURES_BIT(RES4387_FAST_LPO_AVAIL) | in BCMATTACHFN()
7596 PMURES_BIT(RES4387_PMU_LP); in BCMATTACHFN()
7767 uint32 deps = PMURES_BIT(rsrc_num) | in BCMATTACHFN()
7768 si_pmu_res_deps(sih, osh, pmu, PMURES_BIT(rsrc_num), TRUE); in BCMATTACHFN()
7790 PMURES_BIT(RES4389_FAST_LPO_AVAIL) | in BCMATTACHFN()
7791 PMURES_BIT(RES4389_PMU_LP); in BCMATTACHFN()
8795 min_mask = PMURES_BIT(RES4369_LDO3P3_PU); in si_pmu_min_res_ldo3p3_set()
8806 min_mask = PMURES_BIT(RES4378_LDO3P3_PU); in si_pmu_min_res_ldo3p3_set()
8833 min_mask = PMURES_BIT(rsc->otp_pu); in si_pmu_min_res_otp_pu_set()
9845 if (PMU_REG(sih, res_state, 0, 0) & PMURES_BIT(RES4387_PWRSW_MAIN)) { in si_pmu_res_state_pwrsw_main_wait()
9847 PMURES_BIT(RES4387_PWRSW_MAIN)), 10000); in si_pmu_res_state_pwrsw_main_wait()
9850 ret = (PMU_REG(sih, res_state, 0, 0) & PMURES_BIT(RES4387_PWRSW_MAIN)) ? in si_pmu_res_state_pwrsw_main_wait()
9927 SPINWAIT(!(PMU_REG(sih, res_state, 0, 0) & PMURES_BIT(rsrc)), PMU_MAX_TRANSITION_DLY); in si_pmu_res_state_wait()
9928 ASSERT(PMU_REG(sih, res_state, 0, 0) & PMURES_BIT(rsrc)); in si_pmu_res_state_wait()