5969 	uint32 otps = 0u;  in si_pmu_otp_is_ready()
5972 		otps = si_corereg(sih, si_findcoreidx(sih, GCI_CORE_ID, 0u),  in si_pmu_otp_is_ready()
5973 			OFFSETOF(gciregs_t, otpstatus), 0u, 0u);  in si_pmu_otp_is_ready()
5975 		otps = si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, otpstatus), 0u, 0u);  in si_pmu_otp_is_ready()
6065 			on ? 0u : OTPC_FORCE_OTP_PWR_DIS);  in si_pmu_otp_power()
6237 		st = (!(si_gci_direct(sih, GCI_OFFSETOF(sih, otpcontrol), 0u, 0u) &  in si_pmu_is_otp_powered()
7728 				0u << GCI_CC28_IHRP_SEL_SHIFT);  in BCMATTACHFN()
7741 				0u << GCI_CC28_IHRP_SEL_SHIFT);  in BCMATTACHFN()
7917 				0u << GCI_CC28_IHRP_SEL_SHIFT);  in BCMATTACHFN()
8645 	uint32 bt_or_wl = 0u;  in si_pmu_ldo3p3_soft_start_wl_get()
8715 	if (en_val == 0u) {  in si_pmu_ldo3p3_soft_start_get()
8730 	uint32 bt_or_wl = 0u;  in si_pmu_ldo3p3_soft_start_wl_set()
8746 	uint32 dis_val = en_val ? 0u : 1u;  in si_pmu_ldo3p3_soft_start_set()
8752 	if (slew_rate != (uint32)(~0u)) {  in si_pmu_ldo3p3_soft_start_set()
8777 		si_pmu_vreg_control(sih, val_reg, (val_mask << val_shift), 0u);  in si_pmu_ldo3p3_soft_start_set()