Lines Matching +full:0 +full:x0000001
241 /* But 0 is a valid resource number! */
242 #define NO_SUCH_RESOURCE 0 /**< means: chip does not have such a PMU resource */
245 #define PMU_PLL_CTRL_REG0 0
265 #define OTP_XTAL_BIAS_CAL_DONE_4378_WRD_MASK 0x1
268 #define OTP_XTAL_BIAS_VAL_4378_WRD_SHIFT 0
269 #define OTP_XTAL_BIAS_VAL_4378_WRD_MASK 0xFF
272 /* changes the drive strength of gpio_12 and gpio_14 from 0x3 to 0x01 */
273 #define GPIO_DRIVE_4378_MASK 0x3Fu
274 #define GPIO_DRIVE_4378_VAL 0x09u
382 ASSERT(0); in BCMRAMFN()
428 uint8 pll_ctrlcnt = 0; in BCMATTACHFN()
440 for (i = 0; i < pll_ctrlcnt; i++) { in BCMATTACHFN()
445 val = (uint32)bcm_strtoul(otp_val, NULL, 0); in BCMATTACHFN()
446 si_pmu_pllcontrol(sih, i, ~0, val); in BCMATTACHFN()
461 uint8 vreg_ctrlcnt = 0; in BCMATTACHFN()
473 for (i = 0; i < vreg_ctrlcnt; i++) { in BCMATTACHFN()
478 val = (uint32)bcm_strtoul(otp_val, NULL, 0); in BCMATTACHFN()
479 si_pmu_vreg_control(sih, i, ~0, val); in BCMATTACHFN()
503 for (i = 0; i < cc_ctrlcnt; i++) { in BCMATTACHFN()
508 val = (uint32)bcm_strtoul(otp_val, NULL, 0); in BCMATTACHFN()
509 si_pmu_chipcontrol(sih, i, 0xFFFFFFFF, val); /* writes to PMU chipctrl reg 'i' */ in BCMATTACHFN()
521 uint8 sr_cntl_shift = 0, rc_shift = 0, shift = 0, mask = 0; in si_pmu_set_ldo_voltage()
522 uint8 addr = 0; in si_pmu_set_ldo_voltage()
523 uint8 do_reg2 = 0, rshift2 = 0, rc_shift2 = 0, mask2 = 0, addr2 = 0; in si_pmu_set_ldo_voltage()
537 rc_shift = 0; in si_pmu_set_ldo_voltage()
538 mask = 0xf; in si_pmu_set_ldo_voltage()
548 addr = 0; in si_pmu_set_ldo_voltage()
550 mask = 0x7; in si_pmu_set_ldo_voltage()
554 mask2 = 0x8; in si_pmu_set_ldo_voltage()
569 ~0, addr); in si_pmu_set_ldo_voltage()
573 /* rshift2 - right shift moves mask2 to bit 0, rc_shift2 - left shift in reg */ in si_pmu_set_ldo_voltage()
613 if (ilp != 0) { in BCMINITFN()
623 if (ilp != 0) { in BCMINITFN()
669 pmu = si_setcore(sih, PMU_CORE_ID, 0); in BCMINITFN()
685 if (macunit == 0) { in BCMINITFN()
692 ASSERT(0); in BCMINITFN()
699 if (macunit == 0) { in BCMINITFN()
709 ASSERT(0); in BCMINITFN()
737 pmu = si_setcore(sih, PMU_CORE_ID, 0); in BCMINITFN()
757 uint delay = 0; in BCMINITFN()
797 #define RES_DEPEND_SET 0 /* Override the dependencies mask */
803 {RES43012_MEMLPLDO_PU, 0x00200020},
804 {RES43012_PMU_SLEEP, 0x00a600a6},
805 {RES43012_FAST_LPO, 0x00D20000},
806 {RES43012_BTLPO_3P3, 0x007D0000},
807 {RES43012_SR_POK, 0x00c80000},
808 {RES43012_DUMMY_PWRSW, 0x01400000},
809 {RES43012_DUMMY_LDO3P3, 0x00000000},
810 {RES43012_DUMMY_BT_LDO3P3, 0x00000000},
811 {RES43012_DUMMY_RADIO, 0x00000000},
812 {RES43012_VDDB_VDDRET, 0x0020000a},
813 {RES43012_HV_LDO3P3, 0x002C0000},
814 {RES43012_XTAL_PU, 0x04000000},
815 {RES43012_SR_CLK_START, 0x00080000},
816 {RES43012_XTAL_STABLE, 0x00000000},
817 {RES43012_FCBS, 0x00000000},
818 {RES43012_CBUCK_MODE, 0x00000000},
819 {RES43012_CORE_READY, 0x00000000},
820 {RES43012_ILP_REQ, 0x00000000},
821 {RES43012_ALP_AVAIL, 0x00280008},
822 {RES43012_RADIOLDO_1P8, 0x00220000},
823 {RES43012_MINI_PMU, 0x00220000},
824 {RES43012_SR_SAVE_RESTORE, 0x02600260},
825 {RES43012_PHY_PWRSW, 0x00800005},
826 {RES43012_VDDB_CLDO, 0x0020000a},
827 {RES43012_SUBCORE_PWRSW, 0x0060000a},
828 {RES43012_SR_SLEEP, 0x00000000},
829 {RES43012_HT_START, 0x00A00000},
830 {RES43012_HT_AVAIL, 0x00000000},
831 {RES43012_MACPHY_CLK_AVAIL, 0x00000000},
835 {RES4360_BBPLLPWRSW_PU, 0x00200001}
839 {RES43602_SR_SAVE_RESTORE, 0x00190019},
840 {RES43602_XTAL_PU, 0x00280002},
841 {RES43602_RFLDO_PU, 0x00430005}
845 {0, 0, 0, NULL}
976 {RES4360_XTAL_PU, 0x00430002}, /* Changed for 4360B1 */
980 {PMURES_BIT(RES4369_DUMMY), RES_DEPEND_SET, 0x00000000, NULL},
981 {PMURES_BIT(RES4369_ABUCK), RES_DEPEND_SET, 0x00000005, NULL},
982 {PMURES_BIT(RES4369_PMU_SLEEP), RES_DEPEND_SET, 0x00000001, NULL},
983 {PMURES_BIT(RES4369_MISCLDO), RES_DEPEND_SET, 0x00000007, NULL},
984 {PMURES_BIT(RES4369_LDO3P3), RES_DEPEND_SET, 0x00000001, NULL},
985 {PMURES_BIT(RES4369_FAST_LPO_AVAIL), RES_DEPEND_SET, 0x00000005, NULL},
986 {PMURES_BIT(RES4369_XTAL_PU), RES_DEPEND_SET, 0x00000007, NULL},
987 {PMURES_BIT(RES4369_XTAL_STABLE), RES_DEPEND_SET, 0x00000047, NULL},
988 {PMURES_BIT(RES4369_PWRSW_DIG), RES_DEPEND_SET, 0x060000cf, NULL},
989 {PMURES_BIT(RES4369_SR_DIG), RES_DEPEND_SET, 0x060001cf, NULL},
990 {PMURES_BIT(RES4369_SLEEP_DIG), RES_DEPEND_SET, 0x060003cf, NULL},
991 {PMURES_BIT(RES4369_PWRSW_AUX), RES_DEPEND_SET, 0x040000cf, NULL},
992 {PMURES_BIT(RES4369_SR_AUX), RES_DEPEND_SET, 0x040008cf, NULL},
993 {PMURES_BIT(RES4369_SLEEP_AUX), RES_DEPEND_SET, 0x040018cf, NULL},
994 {PMURES_BIT(RES4369_PWRSW_MAIN), RES_DEPEND_SET, 0x040000cf, NULL},
995 {PMURES_BIT(RES4369_SR_MAIN), RES_DEPEND_SET, 0x040040cf, NULL},
996 {PMURES_BIT(RES4369_SLEEP_MAIN), RES_DEPEND_SET, 0x0400c0cf, NULL},
997 {PMURES_BIT(RES4369_DIG_CORE_RDY), RES_DEPEND_SET, 0x060007cf, NULL},
998 {PMURES_BIT(RES4369_CORE_RDY_AUX), RES_DEPEND_SET, 0x040038cf, NULL},
999 {PMURES_BIT(RES4369_ALP_AVAIL), RES_DEPEND_SET, 0x060207cf, NULL},
1000 {PMURES_BIT(RES4369_RADIO_AUX_PU), RES_DEPEND_SET, 0x040438df, NULL},
1001 {PMURES_BIT(RES4369_MINIPMU_AUX_PU), RES_DEPEND_SET, 0x041438df, NULL},
1002 {PMURES_BIT(RES4369_CORE_RDY_MAIN), RES_DEPEND_SET, 0x0401c0cf, NULL},
1003 {PMURES_BIT(RES4369_RADIO_MAIN_PU), RES_DEPEND_SET, 0x0441c0df, NULL},
1004 {PMURES_BIT(RES4369_MINIPMU_MAIN_PU), RES_DEPEND_SET, 0x04c1c0df, NULL},
1005 {PMURES_BIT(RES4369_PCIE_EP_PU), RES_DEPEND_SET, 0x040000cf, NULL},
1006 {PMURES_BIT(RES4369_COLD_START_WAIT), RES_DEPEND_SET, 0x0000000f, NULL},
1007 {PMURES_BIT(RES4369_ARMHTAVAIL), RES_DEPEND_SET, 0x060a07cf, NULL},
1008 {PMURES_BIT(RES4369_HT_AVAIL), RES_DEPEND_SET, 0x060a07cf, NULL},
1009 {PMURES_BIT(RES4369_MACPHY_AUX_CLK_AVAIL), RES_DEPEND_SET, 0x163e3fdf, NULL},
1010 {PMURES_BIT(RES4369_MACPHY_MAIN_CLK_AVAIL), RES_DEPEND_SET, 0x17cbc7df, NULL},
1014 {PMURES_BIT(RES4369_DUMMY), RES_DEPEND_SET, 0x00000000, NULL},
1015 {PMURES_BIT(RES4369_ABUCK), RES_DEPEND_SET, 0x00000005, NULL},
1016 {PMURES_BIT(RES4369_PMU_SLEEP), RES_DEPEND_SET, 0x00000001, NULL},
1017 {PMURES_BIT(RES4369_MISCLDO), RES_DEPEND_SET, 0x00000007, NULL},
1018 {PMURES_BIT(RES4369_LDO3P3), RES_DEPEND_SET, 0x00000001, NULL},
1019 {PMURES_BIT(RES4369_FAST_LPO_AVAIL), RES_DEPEND_SET, 0x00000005, NULL},
1020 {PMURES_BIT(RES4369_XTAL_PU), RES_DEPEND_SET, 0x00000007, NULL},
1021 {PMURES_BIT(RES4369_XTAL_STABLE), RES_DEPEND_SET, 0x00000047, NULL},
1022 {PMURES_BIT(RES4369_PWRSW_DIG), RES_DEPEND_SET, 0x060000ef, NULL},
1023 {PMURES_BIT(RES4369_SR_DIG), RES_DEPEND_SET, 0x060001ef, NULL},
1024 {PMURES_BIT(RES4369_SLEEP_DIG), RES_DEPEND_SET, 0x060003ef, NULL},
1025 {PMURES_BIT(RES4369_PWRSW_AUX), RES_DEPEND_SET, 0x040000ef, NULL},
1026 {PMURES_BIT(RES4369_SR_AUX), RES_DEPEND_SET, 0x040008ef, NULL},
1027 {PMURES_BIT(RES4369_SLEEP_AUX), RES_DEPEND_SET, 0x040018ef, NULL},
1028 {PMURES_BIT(RES4369_PWRSW_MAIN), RES_DEPEND_SET, 0x040000ef, NULL},
1029 {PMURES_BIT(RES4369_SR_MAIN), RES_DEPEND_SET, 0x040040ef, NULL},
1030 {PMURES_BIT(RES4369_SLEEP_MAIN), RES_DEPEND_SET, 0x0400c0ef, NULL},
1031 {PMURES_BIT(RES4369_DIG_CORE_RDY), RES_DEPEND_SET, 0x060007ef, NULL},
1032 {PMURES_BIT(RES4369_CORE_RDY_AUX), RES_DEPEND_SET, 0x040038ef, NULL},
1033 {PMURES_BIT(RES4369_ALP_AVAIL), RES_DEPEND_SET, 0x060207ef, NULL},
1034 {PMURES_BIT(RES4369_RADIO_AUX_PU), RES_DEPEND_SET, 0x040438ff, NULL},
1035 {PMURES_BIT(RES4369_MINIPMU_AUX_PU), RES_DEPEND_SET, 0x041438ff, NULL},
1036 {PMURES_BIT(RES4369_CORE_RDY_MAIN), RES_DEPEND_SET, 0x0401c0ef, NULL},
1037 {PMURES_BIT(RES4369_RADIO_MAIN_PU), RES_DEPEND_SET, 0x0441c0ff, NULL},
1038 {PMURES_BIT(RES4369_MINIPMU_MAIN_PU), RES_DEPEND_SET, 0x04c1c0ff, NULL},
1039 {PMURES_BIT(RES4369_PCIE_EP_PU), RES_DEPEND_SET, 0x0400002f, NULL},
1040 {PMURES_BIT(RES4369_COLD_START_WAIT), RES_DEPEND_SET, 0x0000002f, NULL},
1041 {PMURES_BIT(RES4369_ARMHTAVAIL), RES_DEPEND_SET, 0x060a07ef, NULL},
1042 {PMURES_BIT(RES4369_HT_AVAIL), RES_DEPEND_SET, 0x060a07ef, NULL},
1043 {PMURES_BIT(RES4369_MACPHY_AUX_CLK_AVAIL), RES_DEPEND_SET, 0x163e3fff, NULL},
1044 {PMURES_BIT(RES4369_MACPHY_MAIN_CLK_AVAIL), RES_DEPEND_SET, 0x17cbc7ff, NULL},
1048 {RES4369_DUMMY, 0x00220022},
1049 {RES4369_ABUCK, 0x00c80022},
1050 {RES4369_PMU_SLEEP, 0x00c80022},
1051 {RES4369_MISCLDO, 0x00bd0022},
1052 {RES4369_LDO3P3, 0x00bd0022},
1053 {RES4369_FAST_LPO_AVAIL, 0x01500022},
1054 {RES4369_XTAL_PU, 0x07d00022},
1055 {RES4369_XTAL_STABLE, 0x00220022},
1056 {RES4369_PWRSW_DIG, 0x02100087},
1057 {RES4369_SR_DIG, 0x02000200},
1058 {RES4369_SLEEP_DIG, 0x00220022},
1059 {RES4369_PWRSW_AUX, 0x03900087},
1060 {RES4369_SR_AUX, 0x01cc01cc},
1061 {RES4369_SLEEP_AUX, 0x00220022},
1062 {RES4369_PWRSW_MAIN, 0x03900087},
1063 {RES4369_SR_MAIN, 0x02000200},
1064 {RES4369_SLEEP_MAIN, 0x00220022},
1065 {RES4369_DIG_CORE_RDY, 0x00220044},
1066 {RES4369_CORE_RDY_AUX, 0x00220044},
1067 {RES4369_ALP_AVAIL, 0x00220044},
1068 {RES4369_RADIO_AUX_PU, 0x006e0022},
1069 {RES4369_MINIPMU_AUX_PU, 0x00460022},
1070 {RES4369_CORE_RDY_MAIN, 0x00220022},
1071 {RES4369_RADIO_MAIN_PU, 0x006e0022},
1072 {RES4369_MINIPMU_MAIN_PU, 0x00460022},
1073 {RES4369_PCIE_EP_PU, 0x02100087},
1074 {RES4369_COLD_START_WAIT, 0x00220022},
1075 {RES4369_ARMHTAVAIL, 0x00a80022},
1077 {RES4369_MACPHY_AUX_CLK_AVAIL, 0x00640022},
1078 {RES4369_MACPHY_MAIN_CLK_AVAIL, 0x00640022},
1082 {RES4369_DUMMY, 0x00220022},
1083 {RES4369_ABUCK, 0x00c80022},
1084 {RES4369_PMU_SLEEP, 0x00c80022},
1085 {RES4369_MISCLDO, 0x00bd0022},
1086 {RES4369_LDO3P3, 0x00bd0022},
1087 {RES4369_FAST_LPO_AVAIL, 0x01500022},
1088 {RES4369_XTAL_PU, 0x07d00022},
1089 {RES4369_XTAL_STABLE, 0x00220022},
1090 {RES4369_PWRSW_DIG, 0x02100087},
1091 {RES4369_SR_DIG, 0x02000200},
1092 {RES4369_SLEEP_DIG, 0x00220022},
1093 {RES4369_PWRSW_AUX, 0x03900087},
1094 {RES4369_SR_AUX, 0x01cc01cc},
1095 {RES4369_SLEEP_AUX, 0x00220022},
1096 {RES4369_PWRSW_MAIN, 0x03900087},
1097 {RES4369_SR_MAIN, 0x02000200},
1098 {RES4369_SLEEP_MAIN, 0x00220022},
1099 {RES4369_DIG_CORE_RDY, 0x00220044},
1100 {RES4369_CORE_RDY_AUX, 0x00220044},
1101 {RES4369_ALP_AVAIL, 0x00220044},
1102 {RES4369_RADIO_AUX_PU, 0x006e0022},
1103 {RES4369_MINIPMU_AUX_PU, 0x00460022},
1104 {RES4369_CORE_RDY_MAIN, 0x00220022},
1105 {RES4369_RADIO_MAIN_PU, 0x006e0022},
1106 {RES4369_MINIPMU_MAIN_PU, 0x00460022},
1107 {RES4369_PCIE_EP_PU, 0x01200087},
1108 {RES4369_COLD_START_WAIT, 0x00220022},
1109 {RES4369_ARMHTAVAIL, 0x00a80022},
1111 {RES4369_MACPHY_AUX_CLK_AVAIL, 0x00640022},
1112 {RES4369_MACPHY_MAIN_CLK_AVAIL, 0x00640022},
1116 {RES4369_DUMMY, 0x00220022},
1117 {RES4369_ABUCK, 0x00c80022},
1118 {RES4369_PMU_SLEEP, 0x00c80022},
1119 {RES4369_MISCLDO, 0x00bd0022},
1120 {RES4369_LDO3P3, 0x01ad0022},
1121 {RES4369_FAST_LPO_AVAIL, 0x01500022},
1122 {RES4369_XTAL_PU, 0x05dc0022},
1123 {RES4369_XTAL_STABLE, 0x00220022},
1124 {RES4369_PWRSW_DIG, 0x02100087},
1125 {RES4369_SR_DIG, 0x00A000A0},
1126 {RES4369_SLEEP_DIG, 0x00220022},
1127 {RES4369_PWRSW_AUX, 0x03900087},
1128 {RES4369_SR_AUX, 0x01400140},
1129 {RES4369_SLEEP_AUX, 0x00220022},
1130 {RES4369_PWRSW_MAIN, 0x03900087},
1131 {RES4369_SR_MAIN, 0x01A001A0},
1132 {RES4369_SLEEP_MAIN, 0x00220022},
1133 {RES4369_DIG_CORE_RDY, 0x00220044},
1134 {RES4369_CORE_RDY_AUX, 0x00220044},
1135 {RES4369_ALP_AVAIL, 0x00220044},
1136 {RES4369_RADIO_AUX_PU, 0x006e0022},
1137 {RES4369_MINIPMU_AUX_PU, 0x00460022},
1138 {RES4369_CORE_RDY_MAIN, 0x00220022},
1139 {RES4369_RADIO_MAIN_PU, 0x006e0022},
1140 {RES4369_MINIPMU_MAIN_PU, 0x00460022},
1141 {RES4369_PCIE_EP_PU, 0x02100087},
1142 {RES4369_COLD_START_WAIT, 0x00220022},
1143 {RES4369_ARMHTAVAIL, 0x00a80022},
1145 {RES4369_MACPHY_AUX_CLK_AVAIL, 0x00640022},
1146 {RES4369_MACPHY_MAIN_CLK_AVAIL, 0x00640022},
1150 {RES4369_DUMMY, 0x00220022},
1151 {RES4369_ABUCK, 0x00c80022},
1152 {RES4369_PMU_SLEEP, 0x00c80022},
1153 {RES4369_MISCLDO, 0x00bd0022},
1154 {RES4369_LDO3P3, 0x01ad0022},
1155 {RES4369_FAST_LPO_AVAIL, 0x01500022},
1156 {RES4369_XTAL_PU, 0x05dc0022},
1157 {RES4369_XTAL_STABLE, 0x00220022},
1158 {RES4369_PWRSW_DIG, 0x02100087},
1159 {RES4369_SR_DIG, 0x02000200},
1160 {RES4369_SLEEP_DIG, 0x00220022},
1161 {RES4369_PWRSW_AUX, 0x03900087},
1162 {RES4369_SR_AUX, 0x01cc01cc},
1163 {RES4369_SLEEP_AUX, 0x00220022},
1164 {RES4369_PWRSW_MAIN, 0x03900087},
1165 {RES4369_SR_MAIN, 0x02000200},
1166 {RES4369_SLEEP_MAIN, 0x00220022},
1167 {RES4369_DIG_CORE_RDY, 0x00220044},
1168 {RES4369_CORE_RDY_AUX, 0x00220044},
1169 {RES4369_ALP_AVAIL, 0x00220044},
1170 {RES4369_RADIO_AUX_PU, 0x006e0022},
1171 {RES4369_MINIPMU_AUX_PU, 0x00460022},
1172 {RES4369_CORE_RDY_MAIN, 0x00220022},
1173 {RES4369_RADIO_MAIN_PU, 0x006e0022},
1174 {RES4369_MINIPMU_MAIN_PU, 0x00460022},
1175 {RES4369_PCIE_EP_PU, 0x01200087},
1176 {RES4369_COLD_START_WAIT, 0x00220022},
1177 {RES4369_ARMHTAVAIL, 0x00a80022},
1179 {RES4369_MACPHY_AUX_CLK_AVAIL, 0x00640022},
1180 {RES4369_MACPHY_MAIN_CLK_AVAIL, 0x00640022},
1184 {PMURES_BIT(RES4362_DUMMY), RES_DEPEND_SET, 0x00000000, NULL},
1185 {PMURES_BIT(RES4362_ABUCK), RES_DEPEND_SET, 0x00000005, NULL},
1186 {PMURES_BIT(RES4362_PMU_SLEEP), RES_DEPEND_SET, 0x00000001, NULL},
1187 {PMURES_BIT(RES4362_MISCLDO_PU), RES_DEPEND_SET, 0x00000007, NULL},
1188 {PMURES_BIT(RES4362_LDO3P3_PU), RES_DEPEND_SET, 0x00000005, NULL},
1189 {PMURES_BIT(RES4362_FAST_LPO_AVAIL), RES_DEPEND_SET, 0x00000005, NULL},
1190 {PMURES_BIT(RES4362_XTAL_PU), RES_DEPEND_SET, 0x00000007, NULL},
1191 {PMURES_BIT(RES4362_XTAL_STABLE), RES_DEPEND_SET, 0x00000047, NULL},
1192 {PMURES_BIT(RES4362_PWRSW_DIG), RES_DEPEND_SET, 0x060000cf, NULL},
1193 {PMURES_BIT(RES4362_SR_DIG), RES_DEPEND_SET, 0x060001cf, NULL},
1194 {PMURES_BIT(RES4362_SLEEP_DIG), RES_DEPEND_SET, 0x060003cf, NULL},
1195 {PMURES_BIT(RES4362_PWRSW_AUX), RES_DEPEND_SET, 0x040000cf, NULL},
1196 {PMURES_BIT(RES4362_SR_AUX), RES_DEPEND_SET, 0x040008cf, NULL},
1197 {PMURES_BIT(RES4362_SLEEP_AUX), RES_DEPEND_SET, 0x040018cf, NULL},
1198 {PMURES_BIT(RES4362_PWRSW_MAIN), RES_DEPEND_SET, 0x040000cf, NULL},
1199 {PMURES_BIT(RES4362_SR_MAIN), RES_DEPEND_SET, 0x040040cf, NULL},
1200 {PMURES_BIT(RES4362_SLEEP_MAIN), RES_DEPEND_SET, 0x0400c0cf, NULL},
1201 {PMURES_BIT(RES4362_DIG_CORE_RDY), RES_DEPEND_SET, 0x060007cf, NULL},
1202 {PMURES_BIT(RES4362_CORE_RDY_AUX), RES_DEPEND_SET, 0x040038cf, NULL},
1203 {PMURES_BIT(RES4362_ALP_AVAIL), RES_DEPEND_SET, 0x060207cf, NULL},
1204 {PMURES_BIT(RES4362_RADIO_AUX_PU), RES_DEPEND_SET, 0x040438df, NULL},
1205 {PMURES_BIT(RES4362_MINIPMU_AUX_PU), RES_DEPEND_SET, 0x041438df, NULL},
1206 {PMURES_BIT(RES4362_CORE_RDY_MAIN), RES_DEPEND_SET, 0x0401c0cf, NULL},
1207 {PMURES_BIT(RES4362_RADIO_MAIN_PU), RES_DEPEND_SET, 0x0441c0df, NULL},
1208 {PMURES_BIT(RES4362_MINIPMU_MAIN_PU), RES_DEPEND_SET, 0x04c1c0df, NULL},
1209 {PMURES_BIT(RES4362_PCIE_EP_PU), RES_DEPEND_SET, 0x040000cf, NULL},
1210 {PMURES_BIT(RES4362_COLD_START_WAIT), RES_DEPEND_SET, 0x0000000f, NULL},
1211 {PMURES_BIT(RES4362_ARMHTAVAIL), RES_DEPEND_SET, 0x060a07cf, NULL},
1212 {PMURES_BIT(RES4362_HT_AVAIL), RES_DEPEND_SET, 0x060a07cf, NULL},
1213 {PMURES_BIT(RES4362_MACPHY_AUX_CLK_AVAIL), RES_DEPEND_SET, 0x163e3fdf, NULL},
1214 {PMURES_BIT(RES4362_MACPHY_MAIN_CLK_AVAIL), RES_DEPEND_SET, 0x17cbc7df, NULL},
1218 {RES4362_DUMMY, 0x00220022},
1219 {RES4362_ABUCK, 0x00c80022},
1220 {RES4362_PMU_SLEEP, 0x00c80022},
1221 {RES4362_MISCLDO_PU, 0x00bd0022},
1222 {RES4362_LDO3P3_PU, 0x01ad0022},
1223 {RES4362_FAST_LPO_AVAIL, 0x01500022},
1224 {RES4362_XTAL_PU, 0x05dc0022},
1225 {RES4362_XTAL_STABLE, 0x00220022},
1226 {RES4362_PWRSW_DIG, 0x009000ca},
1227 {RES4362_SR_DIG, 0x00A000A0},
1228 {RES4362_SLEEP_DIG, 0x00220022},
1229 {RES4362_PWRSW_AUX, 0x039000ca},
1230 {RES4362_SR_AUX, 0x01400140},
1231 {RES4362_SLEEP_AUX, 0x00220022},
1232 {RES4362_PWRSW_MAIN, 0x039000ca},
1233 {RES4362_SR_MAIN, 0x01a001a0},
1234 {RES4362_SLEEP_MAIN, 0x00220022},
1235 {RES4362_DIG_CORE_RDY, 0x00220044},
1236 {RES4362_CORE_RDY_AUX, 0x00220044},
1237 {RES4362_ALP_AVAIL, 0x00220044},
1238 {RES4362_RADIO_AUX_PU, 0x006e0022},
1239 {RES4362_MINIPMU_AUX_PU, 0x00460022},
1240 {RES4362_CORE_RDY_MAIN, 0x00220022},
1241 {RES4362_RADIO_MAIN_PU, 0x006e0022},
1242 {RES4362_MINIPMU_MAIN_PU, 0x00460022},
1243 {RES4362_PCIE_EP_PU, 0x009000ca},
1244 {RES4362_COLD_START_WAIT, 0x00220022},
1245 {RES4362_ARMHTAVAIL, 0x00a80022},
1246 {RES4362_HT_AVAIL, 0x00a80022},
1247 {RES4362_MACPHY_AUX_CLK_AVAIL, 0x00640022},
1248 {RES4362_MACPHY_MAIN_CLK_AVAIL, 0x00640022},
1252 {RES4378_ABUCK, 0x00c80022},
1253 {RES4378_PMU_SLEEP, 0x011c0022},
1254 {RES4378_MISC_LDO, 0x00c80022},
1255 {RES4378_XTAL_PU, 0x05dc0022},
1256 {RES4378_SR_DIG, 0x00700070},
1257 {RES4378_SR_AUX, 0x01800180},
1258 {RES4378_SR_MAIN, 0x01a001a0},
1259 {RES4378_RADIO_AUX_PU, 0x006e0022},
1260 {RES4378_MINIPMU_AUX_PU, 0x00460022},
1261 {RES4378_RADIO_MAIN_PU, 0x006e0022},
1262 {RES4378_MINIPMU_MAIN_PU, 0x00460022},
1263 {RES4378_CORE_RDY_CB, 0x00220022},
1265 {RES4378_PWRSW_CB, 0x015e00ca},
1267 {RES4378_MACPHY_AUX_CLK_AVAIL, 0x00640022},
1268 {RES4378_MACPHY_MAIN_CLK_AVAIL, 0x00640022},
1272 {PMURES_BIT(RES4378_ABUCK), RES_DEPEND_SET, 0x00000005, NULL},
1273 {PMURES_BIT(RES4378_PMU_SLEEP), RES_DEPEND_SET, 0x00000001, NULL},
1274 {PMURES_BIT(RES4378_MISC_LDO), RES_DEPEND_SET, 0x00000007, NULL},
1275 {PMURES_BIT(RES4378_LDO3P3_PU), RES_DEPEND_SET, 0x00000001, NULL},
1276 {PMURES_BIT(RES4378_FAST_LPO_AVAIL), RES_DEPEND_SET, 0x00000005, NULL},
1277 {PMURES_BIT(RES4378_XTAL_PU), RES_DEPEND_SET, 0x00000007, NULL},
1278 {PMURES_BIT(RES4378_XTAL_STABLE), RES_DEPEND_SET, 0x00000047, NULL},
1279 {PMURES_BIT(RES4378_PWRSW_DIG), RES_DEPEND_SET, 0x060000ef, NULL},
1280 {PMURES_BIT(RES4378_SR_DIG), RES_DEPEND_SET, 0x060001ef, NULL},
1281 {PMURES_BIT(RES4378_SLEEP_DIG), RES_DEPEND_SET, 0x060003ef, NULL},
1282 {PMURES_BIT(RES4378_PWRSW_AUX), RES_DEPEND_SET, 0x060000ef, NULL},
1283 {PMURES_BIT(RES4378_SR_AUX), RES_DEPEND_SET, 0x060008ef, NULL},
1284 {PMURES_BIT(RES4378_SLEEP_AUX), RES_DEPEND_SET, 0x060018ef, NULL},
1285 {PMURES_BIT(RES4378_PWRSW_MAIN), RES_DEPEND_SET, 0x060000ef, NULL},
1286 {PMURES_BIT(RES4378_SR_MAIN), RES_DEPEND_SET, 0x060040ef, NULL},
1287 {PMURES_BIT(RES4378_SLEEP_MAIN), RES_DEPEND_SET, 0x0600c0ef, NULL},
1288 {PMURES_BIT(RES4378_CORE_RDY_DIG), RES_DEPEND_SET, 0x060007ef, NULL},
1289 {PMURES_BIT(RES4378_CORE_RDY_AUX), RES_DEPEND_SET, 0x06023fef, NULL},
1290 {PMURES_BIT(RES4378_ALP_AVAIL), RES_DEPEND_SET, 0x000000c7, NULL},
1291 {PMURES_BIT(RES4378_RADIO_AUX_PU), RES_DEPEND_SET, 0x06063fff, NULL},
1292 {PMURES_BIT(RES4378_MINIPMU_AUX_PU), RES_DEPEND_SET, 0x06163fff, NULL},
1293 {PMURES_BIT(RES4378_CORE_RDY_MAIN), RES_DEPEND_SET, 0x0603c7ef, NULL},
1294 {PMURES_BIT(RES4378_RADIO_MAIN_PU), RES_DEPEND_SET, 0x0643c7ff, NULL},
1295 {PMURES_BIT(RES4378_MINIPMU_MAIN_PU), RES_DEPEND_SET, 0x06c3c7ff, NULL},
1297 {PMURES_BIT(RES4378_CORE_RDY_CB), RES_DEPEND_SET, 0x0400002f, NULL},
1299 {PMURES_BIT(RES4378_CORE_RDY_CB), RES_DEPEND_SET, 0x040000ef, NULL},
1301 {PMURES_BIT(RES4378_PWRSW_CB), RES_DEPEND_SET, 0x0000002f, NULL},
1302 {PMURES_BIT(RES4378_ARMHTAVAIL), RES_DEPEND_SET, 0x000800c7, NULL},
1303 {PMURES_BIT(RES4378_HT_AVAIL), RES_DEPEND_SET, 0x000800c7, NULL},
1304 {PMURES_BIT(RES4378_MACPHY_AUX_CLK_AVAIL), RES_DEPEND_SET, 0x163e3fff, NULL},
1305 {PMURES_BIT(RES4378_MACPHY_MAIN_CLK_AVAIL), RES_DEPEND_SET, 0x17cbc7ff, NULL},
1309 {RES4387_XTAL_PU, 0x012c0033},
1310 {RES4387_PWRSW_DIG, 0x38993899},
1311 {RES4387_PWRSW_AUX, 0x38993899},
1312 {RES4387_PWRSW_SCAN, 0x38993899},
1313 {RES4387_PWRSW_MAIN, 0x38993899},
1314 {RES4387_CORE_RDY_CB, 0x00960033},
1318 {RES4387_PWRSW_DIG, 0, 0x38993800},
1319 {RES4387_PWRSW_DIG, 1, 0x36000600},
1320 {RES4387_PWRSW_DIG, 2, 0x01000002},
1322 {RES4387_PWRSW_AUX, 0, 0x38993800},
1323 {RES4387_PWRSW_AUX, 1, 0x36000600},
1324 {RES4387_PWRSW_AUX, 2, 0x01000002},
1326 {RES4387_PWRSW_SCAN, 0, 0x38993800},
1327 {RES4387_PWRSW_SCAN, 1, 0x36000600},
1328 {RES4387_PWRSW_SCAN, 2, 0x01000002},
1330 {RES4387_PWRSW_MAIN, 0, 0x38993800},
1331 {RES4387_PWRSW_MAIN, 1, 0x36000600},
1332 {RES4387_PWRSW_MAIN, 2, 0x01000002},
1336 {RES4387_PMU_SLEEP, 0x00960022},
1337 {RES4387_MISC_LDO, 0x00320022},
1338 {RES4387_XTAL_HQ, 0x00210021},
1339 {RES4387_XTAL_PU, 0x03e80033},
1340 {RES4387_PWRSW_DIG, 0x04b002bc},
1341 {RES4387_PWRSW_AUX, 0x060e03bc},
1342 {RES4387_PWRSW_SCAN, 0x060e03bc},
1343 {RES4387_PWRSW_MAIN, 0x060e03bc},
1344 {RES4387_CORE_RDY_CB, 0x000a0033},
1345 {RES4387_PWRSW_CB, 0x006400ca},
1349 {RES4387_PWRSW_DIG, 0, 0x04b002bc},
1350 {RES4387_PWRSW_DIG, 1, 0x02500210},
1351 {RES4387_PWRSW_DIG, 2, 0x00a00010},
1353 {RES4387_PWRSW_AUX, 0, 0x060e03ac},
1354 {RES4387_PWRSW_AUX, 1, 0x028a0134},
1355 {RES4387_PWRSW_AUX, 2, 0x00320002},
1357 {RES4387_PWRSW_MAIN, 0, 0x060e03b2},
1358 {RES4387_PWRSW_MAIN, 1, 0x028a0134},
1359 {RES4387_PWRSW_MAIN, 2, 0x00320002},
1361 {RES4387_PWRSW_SCAN, 0, 0x060e03b2},
1362 {RES4387_PWRSW_SCAN, 1, 0x028a0134},
1363 {RES4387_PWRSW_SCAN, 2, 0x00320002},
1367 {PMURES_BIT(RES4387_DUMMY), RES_DEPEND_SET, 0x0, NULL},
1368 {PMURES_BIT(RES4387_RESERVED_1), RES_DEPEND_SET, 0x0, NULL},
1369 {PMURES_BIT(RES4387_PMU_SLEEP), RES_DEPEND_SET, 0x1, NULL},
1370 {PMURES_BIT(RES4387_MISC_LDO), RES_DEPEND_SET, 0x5, NULL},
1371 {PMURES_BIT(RES4387_RESERVED_4), RES_DEPEND_SET, 0x0, NULL},
1372 {PMURES_BIT(RES4387_XTAL_HQ), RES_DEPEND_SET, 0xc5, NULL},
1373 {PMURES_BIT(RES4387_XTAL_PU), RES_DEPEND_SET, 0x5, NULL},
1374 {PMURES_BIT(RES4387_XTAL_STABLE), RES_DEPEND_SET, 0x45, NULL},
1375 {PMURES_BIT(RES4387_PWRSW_DIG), RES_DEPEND_SET, 0x060000CD, NULL},
1376 {PMURES_BIT(RES4387_CORE_RDY_BTMAIN), RES_DEPEND_SET, 0xCD, NULL},
1377 {PMURES_BIT(RES4387_CORE_RDY_BTSC), RES_DEPEND_SET, 0xC5, NULL},
1378 {PMURES_BIT(RES4387_PWRSW_AUX), RES_DEPEND_SET, 0xCD, NULL},
1379 {PMURES_BIT(RES4387_PWRSW_SCAN), RES_DEPEND_SET, 0xCD, NULL},
1380 {PMURES_BIT(RES4387_CORE_RDY_SCAN), RES_DEPEND_SET, 0x060010CD, NULL},
1381 {PMURES_BIT(RES4387_PWRSW_MAIN), RES_DEPEND_SET, 0xCD, NULL},
1382 {PMURES_BIT(RES4387_RESERVED_15), RES_DEPEND_SET, 0x0, NULL},
1383 {PMURES_BIT(RES4387_RESERVED_16), RES_DEPEND_SET, 0x0, NULL},
1384 {PMURES_BIT(RES4387_CORE_RDY_DIG), RES_DEPEND_SET, 0x060001CD, NULL},
1385 {PMURES_BIT(RES4387_CORE_RDY_AUX), RES_DEPEND_SET, 0x060209CD, NULL},
1386 {PMURES_BIT(RES4387_ALP_AVAIL), RES_DEPEND_SET, 0xC5, NULL},
1387 {PMURES_BIT(RES4387_RADIO_PU_AUX), RES_DEPEND_SET, 0x060609CD, NULL},
1388 {PMURES_BIT(RES4387_RADIO_PU_SCAN), RES_DEPEND_SET, 0x060030CD, NULL},
1389 {PMURES_BIT(RES4387_CORE_RDY_MAIN), RES_DEPEND_SET, 0x060241CD, NULL},
1390 {PMURES_BIT(RES4387_RADIO_PU_MAIN), RES_DEPEND_SET, 0x064241CD, NULL},
1391 {PMURES_BIT(RES4387_MACPHY_CLK_SCAN), RES_DEPEND_SET, 0x162830CD, NULL},
1392 {PMURES_BIT(RES4387_CORE_RDY_CB), RES_DEPEND_SET, 0x0400000D, NULL},
1393 {PMURES_BIT(RES4387_PWRSW_CB), RES_DEPEND_SET, 0x0000000D, NULL},
1394 {PMURES_BIT(RES4387_ARMCLK_AVAIL), RES_DEPEND_SET, 0x000800CD, NULL},
1395 {PMURES_BIT(RES4387_HT_AVAIL), RES_DEPEND_SET, 0x000800CD, NULL},
1396 {PMURES_BIT(RES4387_MACPHY_CLK_AUX), RES_DEPEND_SET, 0x161E09ED, NULL},
1397 {PMURES_BIT(RES4387_MACPHY_CLK_MAIN), RES_DEPEND_SET, 0x16CA41ED, NULL},
1401 {RES4387_PMU_SLEEP, 0x02000022},
1402 {RES4387_MISC_LDO, 0x00320022},
1403 {RES4387_SERDES_AFE_RET, 0x00010001},
1404 {RES4387_XTAL_HQ, 0x00210021},
1405 {RES4387_XTAL_PU, 0x03e80033},
1406 {RES4387_PWRSW_DIG, 0x00d20102},
1407 {RES4387_PWRSW_AUX, 0x01c201e2},
1408 {RES4387_PWRSW_SCAN, 0x01020122},
1409 {RES4387_PWRSW_MAIN, 0x02220242},
1410 {RES4387_CORE_RDY_CB, 0x000a0033},
1411 {RES4387_PWRSW_CB, 0x006400ca},
1416 {RES4387_FAST_LPO_AVAIL, 0x00960001},
1418 {RES4387_PMU_SLEEP, 0x00960022},
1419 {RES4387_MISC_LDO, 0x00320022},
1420 {RES4387_XTAL_HQ, 0x00210021},
1421 {RES4387_XTAL_PU, 0x03e80033},
1422 {RES4387_PWRSW_DIG, 0x01320172},
1423 {RES4387_PWRSW_AUX, 0x01c201e2},
1424 {RES4387_PWRSW_SCAN, 0x019201b2},
1425 {RES4387_PWRSW_MAIN, 0x02220242},
1426 {RES4387_CORE_RDY_CB, 0x000a0033},
1427 {RES4387_PWRSW_CB, 0x006400ca},
1431 {RES4387_PWRSW_DIG, 0, 0x01320142},
1432 {RES4387_PWRSW_DIG, 1, 0x00e2005a},
1433 {RES4387_PWRSW_DIG, 2, 0x00c20052},
1434 {RES4387_PWRSW_DIG, 3, 0x00020002},
1436 {RES4387_PWRSW_AUX, 0, 0x01c201b2},
1437 {RES4387_PWRSW_AUX, 1, 0x0172005a},
1438 {RES4387_PWRSW_AUX, 2, 0x01520052},
1439 {RES4387_PWRSW_AUX, 3, 0x00020002},
1441 {RES4387_PWRSW_MAIN, 0, 0x02220212},
1442 {RES4387_PWRSW_MAIN, 1, 0x01d2005a},
1443 {RES4387_PWRSW_MAIN, 2, 0x01b20052},
1444 {RES4387_PWRSW_MAIN, 3, 0x00020002},
1446 {RES4387_PWRSW_SCAN, 0, 0x01920182},
1447 {RES4387_PWRSW_SCAN, 1, 0x0142005a},
1448 {RES4387_PWRSW_SCAN, 2, 0x01220052},
1449 {RES4387_PWRSW_SCAN, 3, 0x00020002},
1453 {PMURES_BIT(RES4387_DUMMY), RES_DEPEND_SET, 0x0, NULL},
1454 {PMURES_BIT(RES4387_FAST_LPO_AVAIL), RES_DEPEND_SET, 0x0, NULL},
1455 {PMURES_BIT(RES4387_PMU_LP), RES_DEPEND_SET, 0x1, NULL},
1456 {PMURES_BIT(RES4387_MISC_LDO), RES_DEPEND_SET, 0x5, NULL},
1457 {PMURES_BIT(RES4387_SERDES_AFE_RET), RES_DEPEND_SET, 0xD, NULL},
1458 {PMURES_BIT(RES4387_XTAL_HQ), RES_DEPEND_SET, 0xC5, NULL},
1459 {PMURES_BIT(RES4387_XTAL_PU), RES_DEPEND_SET, 0x5, NULL},
1460 {PMURES_BIT(RES4387_XTAL_STABLE), RES_DEPEND_SET, 0x45, NULL},
1461 {PMURES_BIT(RES4387_PWRSW_DIG), RES_DEPEND_SET, 0x060000DD, NULL},
1462 {PMURES_BIT(RES4387_CORE_RDY_BTMAIN), RES_DEPEND_SET, 0xCD, NULL},
1463 {PMURES_BIT(RES4387_CORE_RDY_BTSC), RES_DEPEND_SET, 0xC5, NULL},
1464 {PMURES_BIT(RES4387_PWRSW_AUX), RES_DEPEND_SET, 0xCD, NULL},
1465 {PMURES_BIT(RES4387_PWRSW_SCAN), RES_DEPEND_SET, 0xCD, NULL},
1466 {PMURES_BIT(RES4387_CORE_RDY_SCAN), RES_DEPEND_SET, 0x060010DD, NULL},
1467 {PMURES_BIT(RES4387_PWRSW_MAIN), RES_DEPEND_SET, 0xCD, NULL},
1468 {PMURES_BIT(RES4387_XTAL_PM_CLK), RES_DEPEND_SET, 0xC5, NULL},
1469 {PMURES_BIT(RES4387_RESERVED_16), RES_DEPEND_SET, 0x0, NULL},
1470 {PMURES_BIT(RES4387_CORE_RDY_DIG), RES_DEPEND_SET, 0x060001DD, NULL},
1471 {PMURES_BIT(RES4387_CORE_RDY_AUX), RES_DEPEND_SET, 0x060209DD, NULL},
1472 {PMURES_BIT(RES4387_ALP_AVAIL), RES_DEPEND_SET, 0x80C5, NULL},
1473 {PMURES_BIT(RES4387_RADIO_PU_AUX), RES_DEPEND_SET, 0x060609DD, NULL},
1474 {PMURES_BIT(RES4387_RADIO_PU_SCAN), RES_DEPEND_SET, 0x060030DD, NULL},
1475 {PMURES_BIT(RES4387_CORE_RDY_MAIN), RES_DEPEND_SET, 0x060241DD, NULL},
1476 {PMURES_BIT(RES4387_RADIO_PU_MAIN), RES_DEPEND_SET, 0x064241DD, NULL},
1477 {PMURES_BIT(RES4387_MACPHY_CLK_SCAN), RES_DEPEND_SET, 0x1628B0DD, NULL},
1478 {PMURES_BIT(RES4387_CORE_RDY_CB), RES_DEPEND_SET, 0x0400001D, NULL},
1479 {PMURES_BIT(RES4387_PWRSW_CB), RES_DEPEND_SET, 0x0000001D, NULL},
1480 {PMURES_BIT(RES4387_ARMCLK_AVAIL), RES_DEPEND_SET, 0x000880CD, NULL},
1481 {PMURES_BIT(RES4387_HT_AVAIL), RES_DEPEND_SET, 0x000880CD, NULL},
1482 {PMURES_BIT(RES4387_MACPHY_CLK_AUX), RES_DEPEND_SET, 0x161E89FD, NULL},
1483 {PMURES_BIT(RES4387_MACPHY_CLK_MAIN), RES_DEPEND_SET, 0x16CAC1FD, NULL},
1487 {RES4388_XTAL_PU, 0x012c0033},
1488 {RES4388_PWRSW_DIG, 0x38993899},
1489 {RES4388_PWRSW_AUX, 0x38993899},
1490 {RES4388_PWRSW_SCAN, 0x38993899},
1491 {RES4388_PWRSW_MAIN, 0x38993899},
1492 {RES4388_CORE_RDY_CB, 0x00960033},
1496 {RES4388_PWRSW_DIG, 0, 0x38993800},
1497 {RES4388_PWRSW_DIG, 1, 0x36c00600},
1498 {RES4388_PWRSW_DIG, 2, 0x360005a0},
1499 {RES4388_PWRSW_DIG, 3, 0x01000002},
1501 {RES4388_PWRSW_AUX, 0, 0x38993800},
1502 {RES4388_PWRSW_AUX, 1, 0x36c00600},
1503 {RES4388_PWRSW_AUX, 2, 0x360005a0},
1504 {RES4388_PWRSW_AUX, 3, 0x01000002},
1506 {RES4388_PWRSW_MAIN, 0, 0x38993800},
1507 {RES4388_PWRSW_MAIN, 1, 0x36c00600},
1508 {RES4388_PWRSW_MAIN, 2, 0x360005a0},
1509 {RES4388_PWRSW_MAIN, 3, 0x01000002},
1511 {RES4388_PWRSW_SCAN, 0, 0x38993800},
1512 {RES4388_PWRSW_SCAN, 1, 0x33c00600},
1513 {RES4388_PWRSW_SCAN, 2, 0x330005a0},
1514 {RES4388_PWRSW_SCAN, 3, 0x01000002},
1519 {RES4388_FAST_LPO_AVAIL, 0x00960001},
1521 {RES4388_PMU_LP, 0x00960022},
1522 {RES4388_MISC_LDO, 0x00320022},
1523 {RES4388_XTAL_HQ, 0x00210021},
1524 {RES4388_XTAL_PU, 0x03e80033},
1525 {RES4388_PWRSW_DIG, 0x042c0349},
1526 {RES4388_PWRSW_AUX, 0x0740046a},
1527 {RES4388_PWRSW_SCAN, 0x03c802e8},
1528 {RES4388_PWRSW_MAIN, 0x08080532},
1529 {RES4388_CORE_RDY_CB, 0x000a0033},
1530 {RES4388_PWRSW_CB, 0x006400ca},
1531 {RES4388_MACPHY_CLK_MAIN, 0x00860022},
1535 {RES4388_PWRSW_DIG, 0, 0x0428033c},
1536 {RES4388_PWRSW_DIG, 1, 0x028c0210},
1537 {RES4388_PWRSW_DIG, 2, 0x01cc01b0},
1538 {RES4388_PWRSW_DIG, 3, 0x00a00010},
1540 {RES4388_PWRSW_AUX, 0, 0x0740045a},
1541 {RES4388_PWRSW_AUX, 1, 0x03580202},
1542 {RES4388_PWRSW_AUX, 2, 0x02f801a2},
1543 {RES4388_PWRSW_AUX, 3, 0x00a00002},
1545 {RES4388_PWRSW_MAIN, 0, 0x08080522},
1546 {RES4388_PWRSW_MAIN, 1, 0x04200202},
1547 {RES4388_PWRSW_MAIN, 2, 0x03c001a2},
1548 {RES4388_PWRSW_MAIN, 3, 0x00a00002},
1550 {RES4388_PWRSW_SCAN, 0, 0x03c402d8},
1551 {RES4388_PWRSW_SCAN, 1, 0x02280210},
1552 {RES4388_PWRSW_SCAN, 2, 0x016801b0},
1553 {RES4388_PWRSW_SCAN, 3, 0x00a00010},
1557 {PMURES_BIT(RES4388_DUMMY), RES_DEPEND_SET, 0x00000000, NULL},
1558 {PMURES_BIT(RES4388_FAST_LPO_AVAIL), RES_DEPEND_SET, 0x00000000, NULL},
1559 {PMURES_BIT(RES4388_PMU_LP), RES_DEPEND_SET, 0x00000001, NULL},
1560 {PMURES_BIT(RES4388_MISC_LDO), RES_DEPEND_SET, 0x00000005, NULL},
1561 {PMURES_BIT(RES4388_SERDES_AFE_RET), RES_DEPEND_SET, 0x0000000d, NULL},
1562 {PMURES_BIT(RES4388_XTAL_HQ), RES_DEPEND_SET, 0x000000c5, NULL},
1563 {PMURES_BIT(RES4388_XTAL_PU), RES_DEPEND_SET, 0x00000005, NULL},
1564 {PMURES_BIT(RES4388_XTAL_STABLE), RES_DEPEND_SET, 0x00000045, NULL},
1565 {PMURES_BIT(RES4388_PWRSW_DIG), RES_DEPEND_SET, 0x060000dd, NULL},
1566 {PMURES_BIT(RES4388_BTMC_TOP_RDY), RES_DEPEND_SET, 0x000000cd, NULL},
1567 {PMURES_BIT(RES4388_BTSC_TOP_RDY), RES_DEPEND_SET, 0x000000c5, NULL},
1568 {PMURES_BIT(RES4388_PWRSW_AUX), RES_DEPEND_SET, 0x000000cd, NULL},
1569 {PMURES_BIT(RES4388_PWRSW_SCAN), RES_DEPEND_SET, 0x000000cd, NULL},
1570 {PMURES_BIT(RES4388_CORE_RDY_SCAN), RES_DEPEND_SET, 0x060211dd, NULL},
1571 {PMURES_BIT(RES4388_PWRSW_MAIN), RES_DEPEND_SET, 0x000000cd, NULL},
1572 {PMURES_BIT(RES4388_RESERVED_15), RES_DEPEND_SET, 0x00000000, NULL},
1573 {PMURES_BIT(RES4388_RESERVED_16), RES_DEPEND_SET, 0x00000000, NULL},
1574 {PMURES_BIT(RES4388_CORE_RDY_DIG), RES_DEPEND_SET, 0x060001dd, NULL},
1575 {PMURES_BIT(RES4388_CORE_RDY_AUX), RES_DEPEND_SET, 0x060209dd, NULL},
1576 {PMURES_BIT(RES4388_ALP_AVAIL), RES_DEPEND_SET, 0x000000c5, NULL},
1577 {PMURES_BIT(RES4388_RADIO_PU_AUX), RES_DEPEND_SET, 0x060609dd, NULL},
1578 {PMURES_BIT(RES4388_RADIO_PU_SCAN), RES_DEPEND_SET, 0x060231dd, NULL},
1579 {PMURES_BIT(RES4388_CORE_RDY_MAIN), RES_DEPEND_SET, 0x060241dd, NULL},
1580 {PMURES_BIT(RES4388_RADIO_PU_MAIN), RES_DEPEND_SET, 0x064241dd, NULL},
1581 {PMURES_BIT(RES4388_MACPHY_CLK_SCAN), RES_DEPEND_SET, 0x162a31fd, NULL},
1582 {PMURES_BIT(RES4388_CORE_RDY_CB), RES_DEPEND_SET, 0x040000dd, NULL},
1583 {PMURES_BIT(RES4388_PWRSW_CB), RES_DEPEND_SET, 0x000000dd, NULL},
1584 {PMURES_BIT(RES4388_ARMCLKAVAIL), RES_DEPEND_SET, 0x000800cd, NULL},
1585 {PMURES_BIT(RES4388_HT_AVAIL), RES_DEPEND_SET, 0x000800cd, NULL},
1586 {PMURES_BIT(RES4388_MACPHY_CLK_AUX), RES_DEPEND_SET, 0x161e09fd, NULL},
1587 {PMURES_BIT(RES4388_MACPHY_CLK_MAIN), RES_DEPEND_SET, 0x16ca41fd, NULL},
1591 {RES4389_XTAL_PU, 0x012c0033},
1592 {RES4389_PWRSW_DIG, 0x38993899},
1593 {RES4389_PWRSW_AUX, 0x38993899},
1594 {RES4389_PWRSW_SCAN, 0x38993899},
1595 {RES4389_PWRSW_MAIN, 0x38993899},
1596 {RES4389_CORE_RDY_CB, 0x00960033},
1600 {RES4389_PWRSW_DIG, 0, 0x38993800},
1601 {RES4389_PWRSW_DIG, 1, 0x36c00600},
1602 {RES4389_PWRSW_DIG, 2, 0x360005a0},
1603 {RES4389_PWRSW_DIG, 3, 0x01000002},
1605 {RES4389_PWRSW_AUX, 0, 0x38993800},
1606 {RES4389_PWRSW_AUX, 1, 0x36c00600},
1607 {RES4389_PWRSW_AUX, 2, 0x360005a0},
1608 {RES4389_PWRSW_AUX, 3, 0x01000002},
1610 {RES4389_PWRSW_MAIN, 0, 0x38993800},
1611 {RES4389_PWRSW_MAIN, 1, 0x36c00600},
1612 {RES4389_PWRSW_MAIN, 2, 0x360005a0},
1613 {RES4389_PWRSW_MAIN, 3, 0x01000002},
1615 {RES4389_PWRSW_SCAN, 0, 0x38993800},
1616 {RES4389_PWRSW_SCAN, 1, 0x33c00600},
1617 {RES4389_PWRSW_SCAN, 2, 0x330005a0},
1618 {RES4389_PWRSW_SCAN, 3, 0x01000002},
1623 {RES4389_FAST_LPO_AVAIL, 0x001e0001},
1625 {RES4389_PMU_LP, 0x00960022},
1626 {RES4389_MISC_LDO, 0x00320022},
1627 {RES4389_XTAL_HQ, 0x00210021},
1628 {RES4389_XTAL_PU, 0x03e80033},
1629 {RES4389_PWRSW_DIG, 0x042c0349},
1630 {RES4389_PWRSW_AUX, 0x0740046a},
1631 {RES4389_PWRSW_SCAN, 0x03c802e8},
1632 {RES4389_PWRSW_MAIN, 0x08080532},
1633 {RES4389_CORE_RDY_CB, 0x000a0033},
1634 {RES4389_PWRSW_CB, 0x006400ca},
1635 {RES4389_MACPHY_CLK_MAIN, 0x00860022},
1639 {RES4389_PWRSW_DIG, 0, 0x0428033c},
1640 {RES4389_PWRSW_DIG, 1, 0x028c0210},
1641 {RES4389_PWRSW_DIG, 2, 0x01cc01b0},
1642 {RES4389_PWRSW_DIG, 3, 0x00a00010},
1644 {RES4389_PWRSW_AUX, 0, 0x0740045a},
1645 {RES4389_PWRSW_AUX, 1, 0x03580202},
1646 {RES4389_PWRSW_AUX, 2, 0x02f801a2},
1647 {RES4389_PWRSW_AUX, 3, 0x00a00002},
1649 {RES4389_PWRSW_MAIN, 0, 0x08080522},
1650 {RES4389_PWRSW_MAIN, 1, 0x04200202},
1651 {RES4389_PWRSW_MAIN, 2, 0x03c001a2},
1652 {RES4389_PWRSW_MAIN, 3, 0x00a00002},
1654 {RES4389_PWRSW_SCAN, 0, 0x03c402d8},
1655 {RES4389_PWRSW_SCAN, 1, 0x02280210},
1656 {RES4389_PWRSW_SCAN, 2, 0x016801b0},
1657 {RES4389_PWRSW_SCAN, 3, 0x00a00010},
1661 {PMURES_BIT(RES4389_DUMMY), RES_DEPEND_SET, 0x00000000, NULL},
1662 {PMURES_BIT(RES4389_FAST_LPO_AVAIL), RES_DEPEND_SET, 0x00000000, NULL},
1663 {PMURES_BIT(RES4389_PMU_LP), RES_DEPEND_SET, 0x00000001, NULL},
1664 {PMURES_BIT(RES4389_MISC_LDO), RES_DEPEND_SET, 0x00000005, NULL},
1665 {PMURES_BIT(RES4389_SERDES_AFE_RET), RES_DEPEND_SET, 0x0000000d, NULL},
1666 {PMURES_BIT(RES4389_XTAL_HQ), RES_DEPEND_SET, 0x000000c5, NULL},
1667 {PMURES_BIT(RES4389_XTAL_PU), RES_DEPEND_SET, 0x00000005, NULL},
1668 {PMURES_BIT(RES4389_XTAL_STABLE), RES_DEPEND_SET, 0x00000045, NULL},
1669 {PMURES_BIT(RES4389_PWRSW_DIG), RES_DEPEND_SET, 0x060000dd, NULL},
1670 {PMURES_BIT(RES4389_BTMC_TOP_RDY), RES_DEPEND_SET, 0x000000cd, NULL},
1671 {PMURES_BIT(RES4389_BTSC_TOP_RDY), RES_DEPEND_SET, 0x000000c5, NULL},
1672 {PMURES_BIT(RES4389_PWRSW_AUX), RES_DEPEND_SET, 0x000000cd, NULL},
1673 {PMURES_BIT(RES4389_PWRSW_SCAN), RES_DEPEND_SET, 0x000000cd, NULL},
1674 {PMURES_BIT(RES4389_CORE_RDY_SCAN), RES_DEPEND_SET, 0x060211dd, NULL},
1675 {PMURES_BIT(RES4389_PWRSW_MAIN), RES_DEPEND_SET, 0x000000cd, NULL},
1676 {PMURES_BIT(RES4389_RESERVED_15), RES_DEPEND_SET, 0x00000000, NULL},
1677 {PMURES_BIT(RES4389_RESERVED_16), RES_DEPEND_SET, 0x00000000, NULL},
1678 {PMURES_BIT(RES4389_CORE_RDY_DIG), RES_DEPEND_SET, 0x060001dd, NULL},
1679 {PMURES_BIT(RES4389_CORE_RDY_AUX), RES_DEPEND_SET, 0x060209dd, NULL},
1680 {PMURES_BIT(RES4389_ALP_AVAIL), RES_DEPEND_SET, 0x000000c5, NULL},
1681 {PMURES_BIT(RES4389_RADIO_PU_AUX), RES_DEPEND_SET, 0x060609dd, NULL},
1682 {PMURES_BIT(RES4389_RADIO_PU_SCAN), RES_DEPEND_SET, 0x060231dd, NULL},
1683 {PMURES_BIT(RES4389_CORE_RDY_MAIN), RES_DEPEND_SET, 0x060241dd, NULL},
1684 {PMURES_BIT(RES4389_RADIO_PU_MAIN), RES_DEPEND_SET, 0x064241dd, NULL},
1685 {PMURES_BIT(RES4389_MACPHY_CLK_SCAN), RES_DEPEND_SET, 0x162a31fd, NULL},
1686 {PMURES_BIT(RES4389_CORE_RDY_CB), RES_DEPEND_SET, 0x040000dd, NULL},
1687 {PMURES_BIT(RES4389_PWRSW_CB), RES_DEPEND_SET, 0x000000dd, NULL},
1688 {PMURES_BIT(RES4389_ARMCLKAVAIL), RES_DEPEND_SET, 0x000800cd, NULL},
1689 {PMURES_BIT(RES4389_HT_AVAIL), RES_DEPEND_SET, 0x000800cd, NULL},
1690 {PMURES_BIT(RES4389_MACPHY_CLK_AUX), RES_DEPEND_SET, 0x161e09fd, NULL},
1691 {PMURES_BIT(RES4389_MACPHY_CLK_MAIN), RES_DEPEND_SET, 0x16ca41fd, NULL},
1697 uint32 min_mask = 0, max_mask = 0; in si_pmu_avbtimer_enable()
1704 pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_pmu_avbtimer_enable()
1711 CHIPREV(sih->chiprev) >= 0x3) { in si_pmu_avbtimer_enable()
1712 int cst_ht = CST4360_RSRC_INIT_MODE(sih->chipst) & 0x1; in si_pmu_avbtimer_enable()
1713 if (cst_ht == 0) { in si_pmu_avbtimer_enable()
1750 uint32 min_mask = 0, max_mask = 0; in si_pmu_res_masks()
1756 if (CHIPREV(sih->chiprev) >= 0x4) { in si_pmu_res_masks()
1757 min_mask = 0x103; in si_pmu_res_masks()
1762 if (CHIPREV(sih->chiprev) >= 0x3) { in si_pmu_res_masks()
1764 int cst_ht = CST4360_RSRC_INIT_MODE(sih->chipst) & 0x1; in si_pmu_res_masks()
1765 if (cst_ht == 0) in si_pmu_res_masks()
1766 max_mask = 0x1ff; in si_pmu_res_masks()
1803 max_mask = 0x7FFFFFFF; in si_pmu_res_masks()
1806 min_mask = 0x64fffff; in si_pmu_res_masks()
1810 min_mask = 0x0000011; in si_pmu_res_masks()
1812 min_mask = 0x0000001; in si_pmu_res_masks()
1816 max_mask = 0x7FFFFFFF; in si_pmu_res_masks()
1820 min_mask = 0x064fffff; in si_pmu_res_masks()
1824 min_mask = 0x064fffff; in si_pmu_res_masks()
1830 max_mask = 0x7FFFFFFF; in si_pmu_res_masks()
1834 min_mask = 0x64fffff; in si_pmu_res_masks()
1840 min_mask = pmu_corereg(sih, SI_CC_IDX, min_res_mask, 0, 0); in si_pmu_res_masks()
1849 max_mask = 0x7FFFFFFF; in si_pmu_res_masks()
1853 min_mask = 0x64fffff; in si_pmu_res_masks()
1859 min_mask = pmu_corereg(sih, SI_CC_IDX, min_res_mask, 0, 0); in si_pmu_res_masks()
1867 max_mask = 0x7FFFFFFF; in si_pmu_res_masks()
1875 min_mask = 0x64fffff; in si_pmu_res_masks()
1881 min_mask = pmu_corereg(sih, SI_CC_IDX, min_res_mask, 0, 0); in si_pmu_res_masks()
1889 max_mask = 0x7FFFFFFF; in si_pmu_res_masks()
1893 min_mask = 0x64fffff; in si_pmu_res_masks()
1894 max_mask = 0x7FFFFFFF; in si_pmu_res_masks()
1898 min_mask = 0x64fffff; in si_pmu_res_masks()
1904 max_mask = 0x7FFFFFFF; in si_pmu_res_masks()
1938 if (tablesz == 0) in si_pmu_resdeptbl_upd()
1949 for (i = 0; i < rsrcs; i ++) { in si_pmu_resdeptbl_upd()
1951 PMURES_BIT(i)) == 0) in si_pmu_resdeptbl_upd()
1956 PMU_MSG(("Changing rsrc %d res_dep_mask to 0x%x\n", i, in si_pmu_resdeptbl_upd()
1962 PMU_MSG(("Adding 0x%x to rsrc %d res_dep_mask\n", in si_pmu_resdeptbl_upd()
1968 PMU_MSG(("Removing 0x%x from rsrc %d res_dep_mask\n", in si_pmu_resdeptbl_upd()
1974 ASSERT(0); in si_pmu_resdeptbl_upd()
1993 for (i = 0; i < pmu_res_depend_table_sz; i ++) { in BCMATTACHFN()
2010 for (i = 0; i < pmu_res_depend_table_sz; i ++) { in BCMATTACHFN()
2029 for (i = 0; i < pmu_res_depend_table_sz; i ++) { in BCMATTACHFN()
2047 ASSERT(0); in BCMATTACHFN()
2059 uint pmu_res_updown_table_sz = 0; in BCMATTACHFN()
2061 uint pmu_res_subst_trans_tmr_table_sz = 0; in BCMATTACHFN()
2063 uint pmu_res_depend_table_sz = 0; in BCMATTACHFN()
2066 uint pmu_res_depend_pciewar_table_sz[2] = {0, 0}; in BCMATTACHFN()
2068 uint32 min_mask = 0, max_mask = 0; in BCMATTACHFN()
2080 pmu = si_setcore(sih, PMU_CORE_ID, 0); in BCMATTACHFN()
2108 pmu_res_depend_pciewar_table[0] = bcm43602_res_pciewar; in BCMATTACHFN()
2109 pmu_res_depend_pciewar_table_sz[0] = ARRAYSIZE(bcm43602_res_pciewar); in BCMATTACHFN()
2131 if (CHIPREV(sih->chiprev) == 0) { in BCMATTACHFN()
2141 ASSERT(0); in BCMATTACHFN()
2144 if (CHIPREV(sih->chiprev) == 0) { in BCMATTACHFN()
2172 GCI_REG_NEW(sih, bt_smem_control1, (0xFF<<16), 0); in BCMATTACHFN()
2180 PMU_CC14_PCIE_VDDB2VDD_UP_DLY_MASK), 0); in BCMATTACHFN()
2184 PMU_CC15_PCIE_VDDB_FORCE_RPS_PWROK_DELAY_MASK), 0); in BCMATTACHFN()
2188 PMU_CC10_PCIE_RESET1_CNT_SLOW_MASK), 0); in BCMATTACHFN()
2190 GCI_REG_NEW(sih, bt_smem_control0, (0xF<<16), 0); in BCMATTACHFN()
2191 GCI_REG_NEW(sih, bt_smem_control0, (0xF<<24), 0); in BCMATTACHFN()
2340 PMU_MSG(("Changing rsrc %d res_updn_timer to 0x%x\n", in BCMATTACHFN()
2354 for (i = 0; i < rsrcs; i ++) { in BCMATTACHFN()
2359 r_val = (uint32)bcm_strtoul(val, NULL, 0); in BCMATTACHFN()
2360 /* PMUrev = 13, pmu resource updown times are 12 bits(0:11 DT, 16:27 UT) */ in BCMATTACHFN()
2364 uint16 up_time = (r_val >> 8) & 0xFF; in BCMATTACHFN()
2365 r_val &= 0xFF; in BCMATTACHFN()
2378 PMU_MSG(("Changing rsrc %d substate %d res_subst_trans_timer to 0x%x\n", in BCMATTACHFN()
2395 for (i = 0; i < rsrcs; i ++) { in BCMATTACHFN()
2401 W_REG(osh, &pmu->res_dep_mask, (uint32)bcm_strtoul(val, NULL, 0)); in BCMATTACHFN()
2416 for (i = 0; i < ARRAYSIZE(pmu_res_depend_pciewar_table); i++) { in BCMATTACHFN()
2435 max_mask = (uint32)bcm_strtoul(val, NULL, 0); in BCMATTACHFN()
2441 min_mask = (uint32)bcm_strtoul(val, NULL, 0); in BCMATTACHFN()
2450 ((CST4360_RSRC_INIT_MODE(sih->chipst) & 1) == 0)) { in BCMATTACHFN()
2452 si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG6, ~0, 0x09048562); in BCMATTACHFN()
2454 si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG14, ~0, 0x09048562); in BCMATTACHFN()
2459 ((CST4360_RSRC_INIT_MODE(sih->chipst) & 1) == 0)) { in BCMATTACHFN()
2463 si_pmu_chipcontrol(sih, PMU_CHIPCTL1, 0x800, 0x800); in BCMATTACHFN()
2466 si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG6, ~0, 0x080004e2); in BCMATTACHFN()
2467 si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG7, ~0, 0xE); in BCMATTACHFN()
2469 si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG14, ~0, 0x080004e2); in BCMATTACHFN()
2470 si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG15, ~0, 0xE); in BCMATTACHFN()
2480 /* First set the bits which change from 0 to 1 in max, then update the in BCMATTACHFN()
2481 * min_mask register and then reset the bits which change from 1 to 0 in BCMATTACHFN()
2482 * in max. This is required as the bit in MAX should never go to 0 when in BCMATTACHFN()
2484 * be 1 when the corresponding bit in max is still 0. in BCMATTACHFN()
2488 /* First set the bits which change from 0 to 1 in max, then update the in BCMATTACHFN()
2489 * min_mask register and then reset the bits which change from 1 to 0 in BCMATTACHFN()
2490 * in max. This is required as the bit in MAX should never go to 0 when in BCMATTACHFN()
2492 * be 1 when the corresponding bit in max is still 0. in BCMATTACHFN()
2500 PMU_MSG(("Changing min_res_mask to 0x%x\n", min_mask)); in BCMATTACHFN()
2506 PMU_MSG(("Changing max_res_mask to 0x%x\n", max_mask)); in BCMATTACHFN()
2524 pcie_clk_ctl_st = si_corereg(sih, 3, 0x1e0, 0, 0); in BCMATTACHFN()
2525 si_corereg(sih, 3, 0x1e0, ~0, (pcie_clk_ctl_st | CCS_HTAREQ)); in BCMATTACHFN()
2572 {12000, 1, 3, 22, 0x9, 0xFFFFEF},
2573 {13000, 2, 1, 6, 0xb, 0x483483},
2574 {14400, 3, 1, 10, 0xa, 0x1C71C7},
2575 {15360, 4, 1, 5, 0xb, 0x755555},
2576 {16200, 5, 1, 10, 0x5, 0x6E9E06},
2577 {16800, 6, 1, 10, 0x5, 0x3Cf3Cf},
2578 {19200, 7, 1, 4, 0xb, 0x755555},
2579 {19800, 8, 1, 11, 0x4, 0xA57EB},
2580 {20000, 9, 1, 11, 0x4, 0x0},
2581 {24000, 10, 3, 11, 0xa, 0x0},
2582 {25000, 11, 5, 16, 0xb, 0x0},
2583 {26000, 12, 1, 2, 0x10, 0xEC4EC4},
2584 {30000, 13, 3, 8, 0xb, 0x0},
2585 {33600, 14, 1, 2, 0xd, 0x186186},
2586 {38400, 15, 1, 2, 0xb, 0x755555},
2587 {40000, 16, 1, 2, 0xb, 0},
2588 {0, 0, 0, 0, 0, 0}
2592 #define PMU1_XTALTAB0_880_12000K 0
2611 {12000, 1, 3, 44, 0x9, 0xFFFFEF},
2612 {13000, 2, 1, 12, 0xb, 0x483483},
2613 {14400, 3, 1, 20, 0xa, 0x1C71C7},
2614 {15360, 4, 1, 10, 0xb, 0x755555},
2615 {16200, 5, 1, 20, 0x5, 0x6E9E06},
2616 {16800, 6, 1, 20, 0x5, 0x3Cf3Cf},
2617 {19200, 7, 1, 18, 0x5, 0x17B425},
2618 {19800, 8, 1, 22, 0x4, 0xA57EB},
2619 {20000, 9, 1, 22, 0x4, 0x0},
2620 {24000, 10, 3, 22, 0xa, 0x0},
2621 {25000, 11, 5, 32, 0xb, 0x0},
2622 {26000, 12, 1, 4, 0x10, 0xEC4EC4},
2623 {30000, 13, 3, 16, 0xb, 0x0},
2624 {38400, 14, 1, 10, 0x4, 0x955555},
2625 {40000, 15, 1, 4, 0xb, 0},
2626 {0, 0, 0, 0, 0, 0}
2668 {12000, 1, 1, 1, 0x50, 0x0 }, /* array index 0 */
2669 {13000, 2, 1, 1, 0x49, 0xD89D89},
2670 {14400, 3, 1, 1, 0x42, 0xAAAAAA},
2671 {15360, 4, 1, 1, 0x3E, 0x800000},
2672 {16200, 5, 1, 1, 0x3B, 0x425ED0},
2673 {16800, 6, 1, 1, 0x39, 0x249249},
2674 {19200, 7, 1, 1, 0x32, 0x0 },
2675 {19800, 8, 1, 1, 0x30, 0x7C1F07},
2676 {20000, 9, 1, 1, 0x30, 0x0 },
2677 {24000, 10, 1, 1, 0x28, 0x0 },
2678 {25000, 11, 1, 1, 0x26, 0x666666}, /* array index 10 */
2679 {26000, 12, 1, 1, 0x24, 0xEC4EC4},
2680 {30000, 13, 1, 1, 0x20, 0x0 },
2681 {33600, 14, 1, 1, 0x1C, 0x924924},
2682 {37400, 15, 2, 1, 0x33, 0x563EF9},
2683 {38400, 16, 2, 1, 0x32, 0x0 },
2684 {40000, 17, 2, 1, 0x30, 0x0 },
2685 {48000, 18, 2, 1, 0x28, 0x0 },
2686 {52000, 19, 2, 1, 0x24, 0xEC4EC4}, /* array index 18 */
2687 {59970, 20, 0, 0, 0, 0 },
2689 {0, 0, 0, 0, 0, 0 }
2694 {12000, 1, 1, 1, 0x50, 0x40000}, /* array index 0 */
2695 {13000, 2, 1, 1, 0x4A, 0x13B14},
2696 {14400, 3, 1, 1, 0x42, 0xE0000},
2697 {15360, 4, 1, 1, 0x3E, 0xB2000},
2698 {16200, 5, 1, 1, 0x3B, 0x71C72},
2699 {16800, 6, 1, 1, 0x39, 0x52492},
2700 {19200, 7, 1, 1, 0x32, 0x28000},
2701 {19800, 8, 1, 1, 0x30, 0xA2E8C},
2702 {20000, 9, 1, 1, 0x30, 0x26666},
2703 {24000, 10, 1, 1, 0x28, 0x20000},
2704 {25000, 11, 1, 1, 0x26, 0x851EC}, /* array index 10 */
2705 {26000, 12, 1, 1, 0x25, 0x09D8A},
2706 {30000, 13, 1, 1, 0x20, 0x1999A},
2707 {33600, 14, 1, 1, 0x1C, 0xA9249},
2708 {37400, 15, 1, 1, 0x19, 0xBFA86},
2709 {38400, 16, 1, 1, 0x19, 0x14000},
2710 {40000, 17, 1, 1, 0x18, 0x13333},
2711 {48000, 18, 1, 1, 0x14, 0x10000},
2712 {52000, 19, 1, 1, 0x12, 0x84EC5}, /* array index 18 */
2713 {0, 0, 0, 0, 0, 0 }
2718 {12000, 1, 1, 1, 0x50, 0x40000}, /* array index 0 */
2719 {13000, 2, 1, 1, 0x4A, 0x13B14},
2720 {14400, 3, 1, 1, 0x42, 0xE0000},
2721 {15360, 4, 1, 1, 0x3E, 0xB2000},
2722 {16200, 5, 1, 1, 0x3B, 0x71C72},
2723 {16800, 6, 1, 1, 0x39, 0x52492},
2724 {19200, 7, 1, 1, 0x32, 0x28000},
2725 {19800, 8, 1, 1, 0x30, 0xA2E8C},
2726 {20000, 9, 1, 1, 0x30, 0x26666},
2727 {24000, 10, 1, 1, 0x28, 0x20000},
2728 {25000, 11, 1, 1, 0x26, 0x851EC}, /* array index 10 */
2729 {26000, 12, 1, 1, 0x25, 0x09D8A},
2730 {30000, 13, 1, 1, 0x20, 0x1999A},
2731 {33600, 14, 1, 1, 0x1C, 0xA9249},
2732 {37400, 15, 1, 1, 0x19, 0xBFA86},
2733 {38400, 16, 1, 1, 0x19, 0x14000},
2734 {40000, 17, 1, 1, 0x18, 0x13333},
2735 {48000, 18, 1, 1, 0x14, 0x10000},
2736 {52000, 19, 1, 1, 0x12, 0x84EC5}, /* array index 18 */
2737 {0, 0, 0, 0, 0, 0 }
2741 #define PMU1_XTALTAB0_960_12000K 0
2762 #define PMU15_XTALTAB0_12000K 0
2786 {37400, 0, XTALTAB0_960_37400K},
2788 {26000, 0, XTALTAB0_960_26000K},
2789 {24000, 0, XTALTAB0_960_24000K}
2801 /* PLL 0 PLL 1 PLL 2 PLL 3 PLL 4 PLL 5 */
2802 0x072fe811, 0x00800000, 0x00000000, 0x038051e8, 0x00000000, 0x00000000,
2803 0x0e5fd422, 0x00800000, 0x00000000, 0x000011e8, 0x00000000, 0x00000000
2808 /* PLL 0 PLL 1 PLL 2 PLL 3 PLL 4 */
2809 0x07df2411, 0x00800000, 0x00000000, 0x038051e8, 0x00000000,
2810 0x0e5fd422, 0x00800000, 0x00000000, 0x000011e8, 0x00000000,
2811 0x1d89dc12, 0x00800000, 0x00000000, 0x06d04de8, 0x00000000,
2812 0x072fe828, 0x00800000, 0x00000000, 0x06d04de8, 0x00000000
2826 {37400, 0, XTALTAB0_960_37400K}
2837 #define PMU_PLL3_4369B0_DEFAULT 0x006ABF86
2841 /* PLL 0 PLL 1 PLL 2 PLL 3 PLL 4 PLL 5 PLL 6 PLL 7 PLL 8 PLL 9 PLL 10 */
2842 0x15000000, 0x06050603, 0x01910806, PMU_PLL3_4369B0_DEFAULT,
2843 0x00000000, 0x32800000, 0xC7AE00A9, 0x40800000,
2844 0x00000000, 0x00000000, 0x00000000
2858 {37400, 0, XTALTAB0_960_37400K}
2865 #define PMU_PLL3_4362A0_DEFAULT 0x006ABF86
2870 /* PLL 0 PLL 1 PLL 2 PLL 3 PLL 4 PLL 5 PLL 6 PLL 7 PLL 8 PLL 9 PLL 10 */
2871 0x15000000, 0x06050603, 0x01910806, PMU_PLL3_4362A0_DEFAULT,
2872 0x00000000, 0x32800000, 0xC7AE00A9, 0x40800000,
2873 0x00000000, 0x00000000, 0x00000000
2881 {XTAL_FREQ_59970MHZ, 0, XTALTAB0_960_59970K}
2887 /* PLL 0 PLL 1 PLL 2 PLL 3 PLL 4 PLL 5 PLL 6 PLL 7 PLL 8 PLL 9 PLL 10 */
2888 0x29d00000, 0x30100c03, 0x00240c06, 0x597ff060,
2889 0x00000000, 0x00000800, 0x00321d3a, 0x000551ff,
2890 0x00000000, 0x10000000, 0x00000000
2928 ASSERT(0); in BCMPOSTTRAPFN()
2972 ASSERT(0); in BCMPOSTTRAPFN()
2976 static uint32 fvco_4360 = 0;
2988 uint origidx = 0; in BCMPOSTTRAPFN()
3003 pll_reg = si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG10, 0, 0); in BCMPOSTTRAPFN()
3004 p1_div = pll_reg & 0xf; in BCMPOSTTRAPFN()
3005 ndiv_int = (pll_reg >> 7) & 0x1f; in BCMPOSTTRAPFN()
3008 pll_reg = si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG11, 0, 0); in BCMPOSTTRAPFN()
3009 ndiv_frac = pll_reg & 0xfffff; in BCMPOSTTRAPFN()
3018 PMU_ERROR(("p1_div calc returned 0! [%d]\n", __LINE__)); in BCMPOSTTRAPFN()
3019 ROMMABLE_ASSERT(0); in BCMPOSTTRAPFN()
3022 if (p1_div == 0) { in BCMPOSTTRAPFN()
3023 ASSERT(p1_div != 0); in BCMPOSTTRAPFN()
3024 p1_div_scale = 0; in BCMPOSTTRAPFN()
3052 uint origidx = 0; in BCMPOSTTRAPFN()
3062 pll_reg = si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG0, 0, 0); in BCMPOSTTRAPFN()
3070 pll_reg = si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG3, 0, 0); in BCMPOSTTRAPFN()
3081 ROMMABLE_ASSERT(0); in BCMPOSTTRAPFN()
3082 fvco = 0; in BCMPOSTTRAPFN()
3153 ASSERT(0); in BCMPOSTTRAPFN()
3154 return 0; in BCMPOSTTRAPFN()
3183 ASSERT(0); in BCMPOSTTRAPFN()
3186 return 0; in BCMPOSTTRAPFN()
3202 for (xt = si_pmu1_xtaltab0(sih); xt != NULL && xt->fref != 0; xt ++) in BCMPOSTTRAPFN()
3206 if (xt == NULL || xt->fref == 0) in BCMPOSTTRAPFN()
3208 ASSERT(xt != NULL && xt->fref != 0); in BCMPOSTTRAPFN()
3260 ASSERT(0); in si_pmu_htclk_mask()
3320 uint8 indx, reg_offset, xf = 0; in si_pmu_pllctrlreg_update()
3321 uint8 pll_ctrlcnt = 0; in si_pmu_pllctrlreg_update()
3332 for (indx = 0; indx < array_size; indx++) { in si_pmu_pllctrlreg_update()
3342 for (reg_offset = 0; reg_offset < pll_ctrlcnt; reg_offset++) { in si_pmu_pllctrlreg_update()
3343 si_pmu_pllcontrol(sih, reg_offset, ~0, in si_pmu_pllctrlreg_update()
3372 ASSERT(xtal <= 0xFFFFFFFF / 1000); in si_pmu_pll28nm_calc_ndiv()
3378 0); in si_pmu_pll28nm_calc_ndiv()
3421 ASSERT(0); in si_pmu_armpll_freq_upd()
3441 ASSERT(0); in si_pmu_bbpll_freq_upd()
3451 ASSERT(0); in si_pmu_armpll_chmdiv_upd()
3459 uint32 def_xtal = 0; in si_pmu_armpll_write_required()
3460 uint32 def_armclk_mhz = 0; in si_pmu_armpll_write_required()
3505 uint8 xf = 0; in BCMATTACHFN()
3509 uint32 array_size = 0; in BCMATTACHFN()
3513 uint32 xtalfreq = 0; in BCMATTACHFN()
3538 /* CASE3: If the xtal obtained is "0", ie., clock is not measured, then in BCMATTACHFN()
3574 array_size = 0; in BCMATTACHFN()
3581 array_size = 0; in BCMATTACHFN()
3605 pmu = si_setcore(sih, PMU_CORE_ID, 0); in BCMATTACHFN()
3617 xf = si_pmu_pllctrlreg_update(sih, osh, NULL, xtal, 0, pllctrlreg_update, in BCMATTACHFN()
3621 if (xf != 0) { in BCMATTACHFN()
3646 si_pmu_pllctrlreg_update(sih, osh, pmu, xtal, 0, pllctrlreg_update, array_size, in BCMATTACHFN()
3667 si_pmu_armpll_freq_upd(sih, 0, ndiv_int, 0); in BCMATTACHFN()
3686 si_pmu_armpll_freq_upd(sih, 0, ndiv_int, 0); in BCMATTACHFN()
3695 if (xtal != 0) { in BCMATTACHFN()
3697 for (xt = si_pmu1_xtaltab0(sih); xt != NULL && xt->fref != 0; xt ++) in BCMATTACHFN()
3706 if (xt == NULL || xt->fref == 0) { in BCMATTACHFN()
3754 /* Write p1div and p2div to pllcontrol[0] */ in BCMATTACHFN()
3806 pmu = si_setcore(sih, PMU_CORE_ID, 0); in BCMPOSTTRAPFN()
3847 uint32 pmutime_diff = 0, pmutime_val = 0; in BCMPOSTTRAPFN()
3864 * if cond = TRUE, res_pending will be read until it becomes == 0;
3865 * If cond = FALSE, res_pending will be read until it becomes != 0;
3875 uint32 pmutime_prev = 0, pmutime_elapsed = 0, res_pend; in BCMPOSTTRAPFN()
3885 if (res_pend == 0) break; in BCMPOSTTRAPFN()
3887 if (res_pend != 0) break; in BCMPOSTTRAPFN()
3909 * step1: wait till (res_pending !=0) OR pmu_max_trans_timeout.
3916 * resources, res_pending resets to 0 for a short duration of time before
3918 * Note: return 0 is GOOD, 1 is BAD [mainly timeout].
3924 int stat = 0; in BCMPOSTTRAPFN()
3926 uint32 elapsed = 0, pmutime_total_elapsed = 0; in BCMPOSTTRAPFN()
3929 sii->res_pend_count = 0; in BCMPOSTTRAPFN()
3934 /* wait until all resources are settled down [till res_pending becomes 0] */ in BCMPOSTTRAPFN()
3949 * that it pends again. The res_pending goes 0 for 1 ILP clock before in BCMPOSTTRAPFN()
3951 * is 0 for more than 1 ILP clk it means nothing is pending in BCMPOSTTRAPFN()
3969 stat = 0; in BCMPOSTTRAPFN()
3992 uint32 delay = 0; in si_pmu_pll_delay_43012()
4013 for (delay = 0; delay < delay_us; delay++) { in si_pmu_pll_delay_43012()
4026 ASSERT(0); in si_pmu_pll_delay_43012()
4035 uint32 rsrc_ht, total_time = 0; in si_pmu_pll_on_43012()
4037 si_pmu_chipcontrol(sih, PMU_CHIPCTL4, PMUCCTL04_43012_FORCE_BBPLL_PWROFF, 0); in si_pmu_pll_on_43012()
4038 total_time += si_pmu_pll_delay_43012(sih, 2, 0); in si_pmu_pll_on_43012()
4040 PMUCCTL04_43012_FORCE_BBPLL_PWRDN, 0); in si_pmu_pll_on_43012()
4041 total_time += si_pmu_pll_delay_43012(sih, 2, 0); in si_pmu_pll_on_43012()
4042 si_pmu_chipcontrol(sih, PMU_CHIPCTL4, PMUCCTL04_43012_FORCE_BBPLL_ARESET, 0); in si_pmu_pll_on_43012()
4054 total_time += si_pmu_pll_delay_43012(sih, 1, 0); in si_pmu_pll_on_43012()
4059 si_pmu_chipcontrol(sih, PMU_CHIPCTL4, PMUCCTL04_43012_FORCE_BBPLL_DRESET, 0); in si_pmu_pll_on_43012()
4060 total_time += si_pmu_pll_delay_43012(sih, 1, 0); in si_pmu_pll_on_43012()
4061 si_pmu_chipcontrol(sih, PMU_CHIPCTL4, PMUCCTL04_43012_DISABLE_LQ_AVAIL, 0); in si_pmu_pll_on_43012()
4062 si_pmu_chipcontrol(sih, PMU_CHIPCTL4, PMUCCTL04_43012_DISABLE_HT_AVAIL, 0); in si_pmu_pll_on_43012()
4071 uint32 total_time = 0; in si_pmu_pll_off_43012()
4077 total_time += si_pmu_pll_delay_43012(sih, 1, 0); in si_pmu_pll_off_43012()
4084 total_time += si_pmu_pll_delay_43012(sih, 1, 0); in si_pmu_pll_off_43012()
4103 *clk_ctl_st = si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0); in si_pmu_pll_off()
4106 if (ht_req == 0) in si_pmu_pll_off()
4121 0) { in si_pmu_pll_off()
4125 if (((si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0) in si_pmu_pll_off()
4131 SPINWAIT(((si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0) in si_pmu_pll_off()
4133 ASSERT((si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0) in si_pmu_pll_off()
4145 SPINWAIT(((si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0) in si_pmu_pll_off()
4147 ASSERT(!(si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0) in si_pmu_pll_off()
4168 pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_pmu_pll_off_PARR()
4177 *clk_ctl_st = si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0); in si_pmu_pll_off_PARR()
4179 if (ht_req == 0) { in si_pmu_pll_off_PARR()
4199 0) { in si_pmu_pll_off_PARR()
4203 if (((si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0) in si_pmu_pll_off_PARR()
4210 SPINWAIT(((si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0) in si_pmu_pll_off_PARR()
4212 ASSERT((si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0) in si_pmu_pll_off_PARR()
4232 if (ht_req == 0) in si_pmu_pll_on()
4238 if (max_mask_mask != 0) in si_pmu_pll_on()
4241 if (min_mask_mask != 0) in si_pmu_pll_on()
4246 SPINWAIT(((si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0) in si_pmu_pll_on()
4248 ASSERT((si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0) in si_pmu_pll_on()
4255 si_pmu_pll_on_43012(sih, osh, pmu, 0); in si_pmu_pll_on()
4271 uint32 min_mask = 0, max_mask = 0, clk_ctl_st = 0; in BCMATTACHFN()
4273 uint32 otpval = 0, regval = 0; in BCMATTACHFN()
4284 for (i = 0; i < pll_ctrlcnt; i++) { in BCMATTACHFN()
4306 (regval = si_pmu_pllcontrol(sih, 3, 0, 0)) != PMU_PLL3_4369B0_DEFAULT) { in BCMATTACHFN()
4307 PMU_ERROR(("Default PLL3 value 0x%x is not same as programmed" in BCMATTACHFN()
4308 "value 0x%x\n", PMU_PLL3_4369B0_DEFAULT, regval)); in BCMATTACHFN()
4355 otpval = (uint32)bcm_strtoul(otp_val, NULL, 0); in BCMATTACHFN()
4356 if ((regval = si_pmu_pllcontrol(sih, 3, 0, 0)) != otpval) { in BCMATTACHFN()
4357 PMU_ERROR(("PLL3 programming value 0x%x is not same as programmed" in BCMATTACHFN()
4358 "value 0x%x\n", otpval, regval)); in BCMATTACHFN()
4397 si_setcore(sih, SDIOD_CORE_ID, 0); in BCMATTACHFN()
4440 tmp = si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG1, 0, 0); in si_pmu_get_backplaneclkspeed()
4457 uint32 max_mask = 0, min_mask = 0, clk_ctl_st = 0; in si_pmu_update_backplane_clock()
4463 pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_pmu_update_backplane_clock()
4500 tmp = si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG2, 0, 0); in BCMPOSTTRAPFN()
4502 ASSERT(mdiv != 0); in BCMPOSTTRAPFN()
4529 (si_arm_clockratio(sih, 0) == 1) && in BCMPOSTTRAPFN()
4543 tmp = si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG5, 0, 0); in BCMPOSTTRAPFN()
4549 ASSERT(si_arm_clockratio(sih, 0) == 2); in BCMPOSTTRAPFN()
4552 tmp = si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG5, 0, 0); in BCMPOSTTRAPFN()
4564 tmp = si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG1, 0, 0); in BCMPOSTTRAPFN()
4568 tmp = si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG1, 0, 0); in BCMPOSTTRAPFN()
4574 tmp = si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG1, 0, 0); in BCMPOSTTRAPFN()
4580 ASSERT(0); in BCMPOSTTRAPFN()
4584 ASSERT(mdiv != 0); in BCMPOSTTRAPFN()
4587 /* Read p2div/p1div from pllcontrol[0] */ in BCMPOSTTRAPFN()
4588 tmp = si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG0, 0, 0); in BCMPOSTTRAPFN()
4595 tmp = si_pmu_pllcontrol(sih, tmp, 0, 0); in BCMPOSTTRAPFN()
4612 ASSERT(p1div != 0); in BCMPOSTTRAPFN()
4616 tmp = si_pmu_pllcontrol(sih, tmp, 0, 0); in BCMPOSTTRAPFN()
4628 fvco += (fref * ((ndiv_frac & 0xfffff) >> 4)) >> 8; in BCMPOSTTRAPFN()
4641 fvco += (fref * (ndiv_frac & 0xfff)) >> 12; in BCMPOSTTRAPFN()
4680 uint8 mdiv2 = 0; in si_mac_clk()
4681 uint32 mac_clk = 0; in si_mac_clk()
4708 ASSERT(0); in si_mac_clk()
4727 tmp = si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG1, 0, 0); in si_pmu_macdiv_4387()
4729 ASSERT(mdiv != 0); in si_pmu_macdiv_4387()
4758 *div = si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG12, 0, 0) & in si_pmu_fvco_macdiv()
4764 *div = (si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG4, 0, 0) & in si_pmu_fvco_macdiv()
4771 *div = (si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL1, 0, 0) in si_pmu_fvco_macdiv()
4785 *div = (si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL1, 0, 0) in si_pmu_fvco_macdiv()
4820 pmu = si_setcore(sih, PMU_CORE_ID, 0); in BCMPOSTTRAPFN()
4849 pmu = si_setcore(sih, PMU_CORE_ID, 0); in BCMPOSTTRAPFN()
4883 pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_pmu_switch_on_PARLDO()
4914 pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_pmu_switch_off_PARLDO()
4953 if (si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0) in BCMATTACHFN()
4961 p1div_shift = 0; in BCMATTACHFN()
4962 pllctrl2_mask = 0xffffffff; in BCMATTACHFN()
4963 pllctrl3_mask = 0xffffffff; in BCMATTACHFN()
4971 p1div = 0x1; in BCMATTACHFN()
4973 ndiv_mode = (vcofreq_withfrac % (xtalfreq * 10000)) ? 3 : 0; in BCMATTACHFN()
4987 &r1, &r0, vcofreq_withfrac % (xtalfreq * 10000), 1 << 24, 0); in BCMATTACHFN()
5006 frac = 0, /* 24 bits fractional divider */ in si_pmu_get_bb_vcofreq()
5008 uint32 xtal1, vcofrac = 0, vcofreq; in si_pmu_get_bb_vcofreq()
5018 reg = si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG2, 0, 0); in si_pmu_get_bb_vcofreq()
5024 frac = si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG3, 0, 0); in si_pmu_get_bb_vcofreq()
5031 reg = si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG2, 0, 0); in si_pmu_get_bb_vcofreq()
5033 p1div = (reg >> 16) & 0xf; in si_pmu_get_bb_vcofreq()
5034 frac = si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG3, 0, 0) & 0x00fffff; in si_pmu_get_bb_vcofreq()
5040 return 0; in si_pmu_get_bb_vcofreq()
5053 if (ndiv_int == 0) { in si_pmu_get_bb_vcofreq()
5054 ASSERT(0); in si_pmu_get_bb_vcofreq()
5055 return 0; in si_pmu_get_bb_vcofreq()
5058 if ((int)xtal1 > (int)((0xffffffff - vcofrac) / ndiv_int)) { in si_pmu_get_bb_vcofreq()
5060 return 0; in si_pmu_get_bb_vcofreq()
5083 pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_pmu_enb_slow_clk()
5089 /* twiki PmuRev30, OneMhzToggleEn:31, AlpPeriod[23:0] */ in si_pmu_enb_slow_clk()
5091 /* Use AlpPeriod[23:0] only chip default value for PmuRev >= 38 chips in si_pmu_enb_slow_clk()
5097 /* AlpPeriod = ROUND(POWER(2,26)/ALP_CLK_FREQ_IN_MHz,0) */ in si_pmu_enb_slow_clk()
5109 } else { /* twiki PmuRev24, OneMhzToggleEn:16, AlpPeriod[15:0] */ in si_pmu_enb_slow_clk()
5111 val = 0x101B6; in si_pmu_enb_slow_clk()
5113 val = 0x10199; in si_pmu_enb_slow_clk()
5153 pmu = si_setcore(sih, PMU_CORE_ID, 0); in BCMATTACHFN()
5216 pmu = si_setcore(sih, PMU_CORE_ID, 0); in BCMPOSTTRAPFN()
5276 * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
5285 return 0; in BCMPOSTTRAPFN()
5289 if ((m == 0) || (m > 4)) { in BCMPOSTTRAPFN()
5291 return 0; in BCMPOSTTRAPFN()
5314 PMU_NONE(("si_pmu5_clock: p1=%d, p2=%d, ndiv=%d(0x%x), m%d=%d; fc=%d, clock=%d\n", in BCMPOSTTRAPFN()
5340 pmu = si_setcore(sih, PMU_CORE_ID, 0); in BCMPOSTTRAPFN()
5360 mdiv = si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG4, 0, 0); in BCMPOSTTRAPFN()
5362 ASSERT(mdiv != 0); in BCMPOSTTRAPFN()
5413 pmu = si_setcore(sih, PMU_CORE_ID, 0); in BCMPOSTTRAPFN()
5437 0)) { in BCMPOSTTRAPFN()
5456 tmp = si_pmu_chipcontrol(sih, PMU1_PLL0_CHIPCTL1, 0, 0); in BCMPOSTTRAPFN()
5473 uint32 clock = 0; in si_pmu_mem_ca7clock()
5477 ca7regs_t *regs = si_setcore(sih, ARMCA7_CORE_ID, 0); in si_pmu_mem_ca7clock()
5483 fastclk = ((R_REG(osh, ARMREG(regs, clk_ctl_st)) & CCS_ARMFASTCLOCKREQ) != 0); in si_pmu_mem_ca7clock()
5491 ASSERT(0); in si_pmu_mem_ca7clock()
5494 if (mdiv == 0) { in si_pmu_mem_ca7clock()
5495 ASSERT(0); in si_pmu_mem_ca7clock()
5496 clock = 0; in si_pmu_mem_ca7clock()
5524 pmu = si_setcore(sih, PMU_CORE_ID, 0); in BCMINITFN()
5543 0)) { in BCMINITFN()
5568 static uint32 ilpcycles_per_sec = 0;
5591 if (ilpcycles_per_sec == 0) { in BCMINITFN()
5597 pmu = si_setcore(sih, PMU_CORE_ID, 0); in BCMINITFN()
5616 ASSERT(ilpcycles_per_sec != 0); in BCMINITFN()
5629 pmu_corereg(sih, SI_CC_IDX, chipcontrol_addr, ~0, reg); in BCMPOSTTRAPFN()
5641 pmu_corereg(sih, SI_CC_IDX, regcontrol_addr, ~0, reg); in BCMPOSTTRAPFN()
5653 pmu_corereg(sih, SI_CC_IDX, pllcontrol_addr, ~0, reg); in BCMPOSTTRAPFN()
5663 * 'drivestrength': desired pad drive strength in mA. Drive strength of 0 requests tri-state (if
5696 pmu = si_setcore(sih, PMU_CORE_ID, 0); in BCMATTACHFN()
5720 (void)pmu_corereg(sih, SI_CC_IDX, pmuintmask0, 0, 0); in BCMATTACHFN()
5730 uint32 deps = 0; in si_pmu_rsrc_macphy_clk_deps()
5739 pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_pmu_rsrc_macphy_clk_deps()
5747 if (macunit == 0) { in si_pmu_rsrc_macphy_clk_deps()
5756 ASSERT(0); in si_pmu_rsrc_macphy_clk_deps()
5770 uint32 deps = 0; in si_pmu_set_mac_rsrc_req_sc()
5774 uint32 rsrc = 0; in si_pmu_set_mac_rsrc_req_sc()
5778 pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_pmu_set_mac_rsrc_req_sc()
5807 pmu = si_setcore(sih, PMU_CORE_ID, 0); in BCMATTACHFN()
5835 pmu = si_setcore(sih, PMU_CORE_ID, 0); in BCMATTACHFN()
5844 deps = 0; in BCMATTACHFN()
5866 pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_pmu_set_mac_rsrc_req()
5872 if (macunit == 0) { in si_pmu_set_mac_rsrc_req()
5901 uint32 min_mask = 0; in BCMINITFN()
5903 uint32 max_mask = 0; in BCMINITFN()
5909 uptime = (R_REG(osh, &pmu->res_updn_timer) >> 16) & 0x7fff; in BCMINITFN()
5911 uptime = (R_REG(osh, &pmu->res_updn_timer) >> 16) & 0x3ff; in BCMINITFN()
5913 uptime = (R_REG(osh, &pmu->res_updn_timer) >> 8) & 0xff; in BCMINITFN()
5917 for (i = 0; i <= PMURES_MAX_RESNUM; i ++) { in BCMINITFN()
5931 dmax = 0; in BCMINITFN()
5932 for (i = 0; i <= PMURES_MAX_RESNUM; i ++) { in BCMINITFN()
5940 PMU_MSG(("si_pmu_res_uptime: rsrc %u uptime %u(deps 0x%08x uptime %u)\n", in BCMINITFN()
5943 uptrans = pmu_fast_trans_en ? 0 : PMURES_UP_TRANSITION; in BCMINITFN()
5953 uint32 deps = 0; in si_pmu_res_deps()
5956 for (i = 0; i <= PMURES_MAX_RESNUM; i ++) { in si_pmu_res_deps()
5963 return !all ? deps : (deps ? (deps | si_pmu_res_deps(sih, osh, pmu, deps, TRUE)) : 0); in si_pmu_res_deps()
5969 uint32 otps = 0u; in si_pmu_otp_is_ready()
5972 otps = si_corereg(sih, si_findcoreidx(sih, GCI_CORE_ID, 0u), in si_pmu_otp_is_ready()
5973 OFFSETOF(gciregs_t, otpstatus), 0u, 0u); in si_pmu_otp_is_ready()
5975 otps = si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, otpstatus), 0u, 0u); in si_pmu_otp_is_ready()
6003 uint32 rsrcs = 0; /* rsrcs to turn on/off OTP power */ in si_pmu_otp_power()
6017 pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_pmu_otp_power()
6026 * Instead, the chipc register OTPCtrl1 (Offset 0xF4) bit 25 (forceOTPpwrDis) is used. in si_pmu_otp_power()
6031 otpctrl1 = si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, otpcontrol1), 0, 0); in si_pmu_otp_power()
6036 si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, otpcontrol1), ~0, otpctrl1); in si_pmu_otp_power()
6065 on ? 0u : OTPC_FORCE_OTP_PWR_DIS); in si_pmu_otp_power()
6074 if (rsrcs != 0) { in si_pmu_otp_power()
6076 uint32 min_mask = 0; in si_pmu_otp_power()
6087 PMU_MSG(("Adding rsrc 0x%x to min_res_mask\n", min_mask)); in si_pmu_otp_power()
6110 on_check = ((min_mask & rsrcs) != 0); in si_pmu_otp_power()
6112 PMU_MSG(("Removing rsrc 0x%x from min_res_mask\n", min_mask)); in si_pmu_otp_power()
6164 uint32 pllreg5 = si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG5, 0, 0); in si_pmu_pll28nm_fvco()
6165 uint32 pllreg4 = si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG4, 0, 0); in si_pmu_pll28nm_fvco()
6178 } else if (p1div == 0) { in si_pmu_pll28nm_fvco()
6179 /* PLL register read fails, return 0 so caller can retry */ in si_pmu_pll28nm_fvco()
6181 return 0; in si_pmu_pll28nm_fvco()
6188 math_uint64_multiple_add(&r_high, &r_low, xf, ndiv_frac, 0); in si_pmu_pll28nm_fvco()
6192 ASSERT((r_high & 0xFFE00000) == 0); in si_pmu_pll28nm_fvco()
6209 pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_pmu_is_otp_powered()
6230 st = (R_REG(osh, &pmu->res_state) & PMURES_BIT(rsc->otp_pu)) != 0; in si_pmu_is_otp_powered()
6237 st = (!(si_gci_direct(sih, GCI_OFFSETOF(sih, otpcontrol), 0u, 0u) & in si_pmu_is_otp_powered()
6257 uint32 ext_lpo_sel, int_lpo_sel, timeout = 0, in BCMATTACHFN()
6258 ext_lpo_avail = 0, lpo_sel = 0; in BCMATTACHFN()
6269 pmu = si_setcore(sih, PMU_CORE_ID, 0); in BCMATTACHFN()
6281 if (ext_lpo_sel != 0) { in BCMATTACHFN()
6286 ext_lpo_isclock ? 0 : PMU43602_CC2_XTAL32_SEL); in BCMATTACHFN()
6296 while (ext_lpo_avail == 0 && timeout < LPO_SEL_TIMEOUT) { in BCMATTACHFN()
6307 timeout = 0; in BCMATTACHFN()
6318 si_gci_chipcontrol(sih, CHIPCTRLREG6, INT_LPO_SEL, 0x0); in BCMATTACHFN()
6322 while (lpo_sel != 0 && timeout < LPO_SEL_TIMEOUT) { in BCMATTACHFN()
6335 PMU43602_CC2_FORCE_EXT_LPO, 0); in BCMATTACHFN()
6338 si_gci_chipcontrol(sih, CHIPCTRLREG6, EXT_LPO_SEL, 0x0); in BCMATTACHFN()
6347 si_pmu_chipcontrol(sih, PMU_CHIPCTL0, CC_INT_LPO_PU, 0x0); in BCMATTACHFN()
6348 si_gci_chipcontrol(sih, CHIPCTRLREG6, GC_INT_LPO_PU, 0x0); in BCMATTACHFN()
6353 } else if (int_lpo_sel != 0) { in BCMATTACHFN()
6367 si_gci_chipcontrol(sih, CHIPCTRLREG6, EXT_LPO_SEL, 0x0); in BCMATTACHFN()
6372 timeout = 0; in BCMATTACHFN()
6373 while (lpo_sel == 0 && timeout < LPO_SEL_TIMEOUT) { in BCMATTACHFN()
6381 si_gci_chipcontrol(sih, CHIPCTRLREG6, INT_LPO_SEL, 0x0); in BCMATTACHFN()
6384 si_pmu_chipcontrol(sih, PMU_CHIPCTL0, CC_EXT_LPO_PU, 0x0); in BCMATTACHFN()
6385 si_gci_chipcontrol(sih, CHIPCTRLREG6, GC_EXT_LPO_PU, 0x0); in BCMATTACHFN()
6402 int lock = 0; in si_pmu_fast_lpo_locked()
6407 lock = CHIPC_REG(sih, chipstatus, 0, 0) & CST43012_FLL_LOCK; in si_pmu_fast_lpo_locked()
6424 return lock ? 1 : 0; in si_pmu_fast_lpo_locked()
6431 int i = 0, lock = 0; in BCMATTACHFN()
6441 lock = CHIPC_REG(sih, chipstatus, 0, 0) & CST43012_FLL_LOCK; in BCMATTACHFN()
6443 for (i = 0; ((i <= 30) && (!lock)); i++) in BCMATTACHFN()
6445 lock = CHIPC_REG(sih, chipstatus, 0, 0) & CST43012_FLL_LOCK; in BCMATTACHFN()
6453 ROMMABLE_ASSERT(0); in BCMATTACHFN()
6481 for (i = 0; ((i < 300) && (!lock)); i++) { in BCMATTACHFN()
6579 fastlpo_dis = 0; in BCMATTACHFN()
6594 fastlpo_pcie_dis = 0; in BCMATTACHFN()
6630 ASSERT(0); in BCMATTACHFN()
6645 if (BCM4369_CHIP(sih->chip) && (CHIPREV(sih->chiprev) == 0)) { in BCMATTACHFN()
6646 si_pmu_chipcontrol(sih, PMU_CHIPCTL4, PMU_CC4_4369_AUX_PD_MEMLPLDO2VDDB_ON, 0); in BCMATTACHFN()
6648 //JTAG_SEL override. When this bit is set, jtag_sel 0, Required for JTAG writes in BCMATTACHFN()
6650 si_gci_chipcontrol(sih, CC_GCI_CHIPCTRL_06, 0x10, 0x10); in BCMATTACHFN()
6652 si_gci_chipcontrol(sih, CC_GCI_CHIPCTRL_06, 0x10, 0x0); in BCMATTACHFN()
6658 * cbuck rsrc 0 - PWM and abuck rsrc 0 - Auto, rsrc 1 - PWM in BCMATTACHFN()
6661 0x3u << PMU_4369_VREG16_RSRC0_CBUCK_MODE_SHIFT); in BCMATTACHFN()
6663 0x3u << PMU_4369_VREG16_RSRC0_ABUCK_MODE_SHIFT); in BCMATTACHFN()
6665 0x3u << PMU_4369_VREG16_RSRC1_ABUCK_MODE_SHIFT); in BCMATTACHFN()
6667 0x3u << PMU_4369_VREG16_RSRC2_ABUCK_MODE_SHIFT); in BCMATTACHFN()
6671 0x10u << PMU_4369_VREG8_ASR_OVADJ_LPPFM_SHIFT); in BCMATTACHFN()
6673 /* Enable rsrc_en_asr_msk[0] and msk[1] */ in BCMATTACHFN()
6675 0x1u << PMU_4369_VREG13_RSRC_EN0_ASR_SHIFT); in BCMATTACHFN()
6677 0x1u << PMU_4369_VREG13_RSRC_EN1_ASR_SHIFT); in BCMATTACHFN()
6679 0x1u << PMU_4369_VREG13_RSRC_EN2_ASR_SHIFT); in BCMATTACHFN()
6682 0x1u << PMU_4369_VREG14_RSRC_EN_CSR_MASK0_SHIFT); in BCMATTACHFN()
6696 ((CHIPREV(sih->chiprev) == 0) ? 1 : 0) << in BCMATTACHFN()
6699 si_pmu_vreg_control(sih, PMU_VREG_5, PMU_4369_VREG_5_LPLDO_POWER_UP_MASK, 0x0u); in BCMATTACHFN()
6701 0xDu << PMU_4369_VREG_5_MEMLPLDO_OP_VLT_ADJ_CTRL_SHIFT); in BCMATTACHFN()
6703 0xFu << PMU_4369_VREG_5_LPLDO_OP_VLT_ADJ_CTRL_SHIFT); in BCMATTACHFN()
6705 /* Enabale MEMLPLDO ( to enable 0x08)and BTLDO is enabled. At sleep RFLDO is disabled */ in BCMATTACHFN()
6707 0x1u << PMU_4369_VREG_6_MEMLPLDO_POWER_UP_SHIFT); in BCMATTACHFN()
6768 ASSERT(0); in si_set_abuck_mode_4362()
6792 * cbuck rsrc 0 - PWM and abuck rsrc 0 - Auto, rsrc 1 - PWM in BCMATTACHFN()
6795 0x2u << PMU_4369_VREG16_RSRC1_ABUCK_MODE_SHIFT); in BCMATTACHFN()
6799 0x10u << PMU_4369_VREG8_ASR_OVADJ_LPPFM_SHIFT); in BCMATTACHFN()
6801 /* Enable rsrc_en_asr_msk[0] and msk[1] */ in BCMATTACHFN()
6803 0x1u << PMU_4369_VREG13_RSRC_EN0_ASR_SHIFT); in BCMATTACHFN()
6805 0x1u << PMU_4369_VREG13_RSRC_EN1_ASR_SHIFT); in BCMATTACHFN()
6807 0x1u << PMU_4369_VREG13_RSRC_EN2_ASR_SHIFT); in BCMATTACHFN()
6810 0x1u << PMU_4369_VREG14_RSRC_EN_CSR_MASK0_SHIFT); in BCMATTACHFN()
6817 /* Enabale MEMLPLDO ( to enable 0x08)and BTLDO is enabled. At sleep RFLDO is disabled */ in BCMATTACHFN()
6819 0x1u << PMU_4369_VREG_6_MEMLPLDO_POWER_UP_SHIFT); in BCMATTACHFN()
6904 PMU_CC17_SCAN_MEMLPLDO2VDDB_OFF, 0); in BCMATTACHFN()
6926 si_pmu_vreg_control(sih, PMU_VREG_5, VREG5_4387_MISCLDO_PU_MASK, 0); in BCMATTACHFN()
6934 PMU_4387_VREG6_WL_PMU_LV_MODE_MASK, 0); in BCMATTACHFN()
6938 PMU_4387_VREG6_MEMLDO_PU_MASK, 0); in BCMATTACHFN()
6961 0); in BCMATTACHFN()
6964 0); in BCMATTACHFN()
6967 0); in BCMATTACHFN()
6976 0); in BCMATTACHFN()
6987 PMU_CC13_CMN_MEMLPLDO2VDDRET_ON, 0); in BCMATTACHFN()
7019 * cbuck rsrc 0 - PWM and abuck rsrc 0 - Auto, rsrc 1 - PWM in BCMATTACHFN()
7022 0x3u << PMU_4362_VREG16_RSRC0_CBUCK_MODE_SHIFT); in BCMATTACHFN()
7024 si_set_abuck_mode_4362(sih, 0x3u); in BCMATTACHFN()
7028 0x10u << PMU_4362_VREG8_ASR_OVADJ_LPPFM_SHIFT); in BCMATTACHFN()
7030 /* Enable rsrc_en_asr_msk[0] and msk[1] */ in BCMATTACHFN()
7032 0x1u << PMU_4362_VREG13_RSRC_EN0_ASR_SHIFT); in BCMATTACHFN()
7034 0x1u << PMU_4362_VREG13_RSRC_EN1_ASR_SHIFT); in BCMATTACHFN()
7036 0x1u << PMU_4362_VREG13_RSRC_EN2_ASR_SHIFT); in BCMATTACHFN()
7039 0x1u << PMU_4362_VREG14_RSRC_EN_CSR_MASK0_SHIFT); in BCMATTACHFN()
7048 0x1u << PMU_4362_VREG_5_MISCLDO_POWER_UP_SHIFT); in BCMATTACHFN()
7049 si_pmu_vreg_control(sih, PMU_VREG_5, PMU_4362_VREG_5_LPLDO_POWER_UP_MASK, 0x0u); in BCMATTACHFN()
7051 0xBu << PMU_4362_VREG_5_MEMLPLDO_OP_VLT_ADJ_CTRL_SHIFT); in BCMATTACHFN()
7053 /* Enabale MEMLPLDO ( to enable 0x08)and BTLDO is enabled. At sleep RFLDO is disabled */ in BCMATTACHFN()
7055 0x1u << PMU_4362_VREG_6_MEMLPLDO_POWER_UP_SHIFT); in BCMATTACHFN()
7108 pmu = si_setcore(sih, PMU_CORE_ID, 0); in BCMATTACHFN()
7168 PCTL_EXT_REQ_MIRROR_ENAB, 0); in BCMATTACHFN()
7172 0); in BCMATTACHFN()
7183 uint32 rsrc_slp = 0xffffffff; in BCMATTACHFN()
7187 pmu = si_setcore(sih, PMU_CORE_ID, 0); in BCMATTACHFN()
7215 if (rsrc_slp != 0xffffffff) { in BCMATTACHFN()
7232 hnd_pmur = si_setcore(sih, PMU_CORE_ID, 0); in BCMATTACHFN()
7258 si_pmu_chipcontrol(sih, PMU_CHIPCTL2, PMUCCTL02_43012_LHL_TIMER_SELECT, 0); in BCMATTACHFN()
7261 si_pmu_chipcontrol(sih, PMU_CHIPCTL2, PMUCCTL02_43012_RFLDO3P3_PU_FORCE_ON, 0); in BCMATTACHFN()
7262 si_pmu_chipcontrol(sih, PMU_CHIPCTL4, PMUCCTL14_43012_DISABLE_LQ_AVAIL, 0); in BCMATTACHFN()
7266 PMU_REG_NEW(sih, extwakereqmask[0], ~0, si_pmu_rsrc_ht_avail_clk_deps(sih, osh)); in BCMATTACHFN()
7304 0x8 << VREG6_43012_MEMLPLDO_ADJ_SHIFT); in BCMATTACHFN()
7308 0xB << VREG6_43012_LPLDO_ADJ_SHIFT); in BCMATTACHFN()
7311 si_pmu_vreg_control(sih, PMU_VREG_7, VREG7_43012_PWRSW_1P8_PU_MASK, 0); in BCMATTACHFN()
7314 LHL_REG(sih, lhl_top_pwrseq_ctl_adr, ~0, PMU_SLEEP_MODE_0); in BCMATTACHFN()
7326 pmuregs_t *pmu = si_setcore(sih, PMU_CORE_ID, 0); in BCMATTACHFN()
7328 uint32 lhl_tmr_sel = 0; in BCMATTACHFN()
7336 W_REG(osh, &pmu->clkstretch, 0x0fff0fff); in BCMATTACHFN()
7368 0x02u << PMU_4362_VREG8_ASR_OVADJ_LPPFM_SHIFT); in BCMATTACHFN()
7370 0x02u << PMU_4362_VREG8_ASR_OVADJ_PFM_SHIFT); in BCMATTACHFN()
7372 0x02u << PMU_4362_VREG8_ASR_OVADJ_PWM_SHIFT); in BCMATTACHFN()
7395 pmuregs_t *pmu = si_setcore(sih, PMU_CORE_ID, 0); in BCMATTACHFN()
7397 uint32 lhl_tmr_sel = 0; in BCMATTACHFN()
7406 W_REG(osh, &pmu->clkstretch, 0x0fff0fff); in BCMATTACHFN()
7439 if (CHIPREV(sih->chiprev) == 0) { in BCMATTACHFN()
7477 pmuregs_t *pmu = si_setcore(sih, PMU_CORE_ID, 0); in BCMATTACHFN()
7479 uint32 lhl_tmr_sel = 0; in BCMATTACHFN()
7506 0); in BCMATTACHFN()
7560 si_pmu_ldo3p3_soft_start_wl_set(sih, osh, 0x03u); in BCMATTACHFN()
7561 si_pmu_ldo3p3_soft_start_bt_set(sih, osh, 0x03u); in BCMATTACHFN()
7582 pmuregs_t *pmu = si_setcore(sih, PMU_CORE_ID, 0); in BCMATTACHFN()
7584 uint32 lhl_tmr_sel = 0; in BCMATTACHFN()
7632 0); in BCMATTACHFN()
7664 curr_misc_ldo_volt = (si_pmu_regcontrol(sih, PMU_VREG_5, 0, 0) & in BCMATTACHFN()
7691 0xFFFFFFFF, XTAL_HQ_SETTING_4387); in BCMATTACHFN()
7695 0xFFFFFFFF, XTAL_LQ_SETTING_4387); in BCMATTACHFN()
7698 si_pmu_chipcontrol(sih, PMU_CHIPCTL13, PMU_CC13_4387_ENAB_RADIO_REG_CLK, 0); in BCMATTACHFN()
7708 (((GRP_PD_TRIGGER_MASK_4387 >> 1) & 0x1) << /* bit 1 */ in BCMATTACHFN()
7710 (((GRP_PD_TRIGGER_MASK_4387 >> 3) & 0x3FFFFF) << /* bit 24:3 */ in BCMATTACHFN()
7716 (((GRP_PD_TRIGGER_MASK_4387 >> 25) & 0x3F) << /* bits 30:25 */ in BCMATTACHFN()
7728 0u << GCI_CC28_IHRP_SEL_SHIFT); in BCMATTACHFN()
7741 0u << GCI_CC28_IHRP_SEL_SHIFT); in BCMATTACHFN()
7769 W_REG(osh, &pmu->extwakereqmask[0], deps); in BCMATTACHFN()
7782 pmuregs_t *pmu = si_setcore(sih, PMU_CORE_ID, 0); in BCMATTACHFN()
7784 uint32 lhl_tmr_sel = 0; in BCMATTACHFN()
7830 0); in BCMATTACHFN()
7874 0xFFFFFFFF, XTAL_HQ_SETTING_4387); in BCMATTACHFN()
7878 0xFFFFFFFF, XTAL_LQ_SETTING_4387); in BCMATTACHFN()
7881 si_pmu_chipcontrol(sih, PMU_CHIPCTL13, PMU_CC13_4387_ENAB_RADIO_REG_CLK, 0); in BCMATTACHFN()
7891 (((GRP_PD_TRIGGER_MASK_4387 >> 1) & 0x1) << /* bit 1 */ in BCMATTACHFN()
7893 (((GRP_PD_TRIGGER_MASK_4387 >> 3) & 0x3FFFFF) << /* bit 24:3 */ in BCMATTACHFN()
7899 (((GRP_PD_TRIGGER_MASK_4387 >> 25) & 0x3F) << /* bits 30:25 */ in BCMATTACHFN()
7917 0u << GCI_CC28_IHRP_SEL_SHIFT); in BCMATTACHFN()
7977 int32 xtal, array_size = 0, dco_code = 0, origidx = 0, pll_reg = 0, err; in si_pmu_openloop_cal_43012()
7989 pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_pmu_openloop_cal_43012()
7996 if (final_dco_code == 0) { in si_pmu_openloop_cal_43012()
7997 currtemp = (currtemp == 0)?-1: currtemp; in si_pmu_openloop_cal_43012()
8000 OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0) in si_pmu_openloop_cal_43012()
8002 ASSERT((si_corereg(sih, SI_CC_IDX, OFFSETOF(chipcregs_t, clk_ctl_st), 0, 0) in si_pmu_openloop_cal_43012()
8027 pll_reg = si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG1, 0, 0); in si_pmu_openloop_cal_43012()
8028 pll_reg = (pll_reg & (~0x3C000)) | (0x4<<14); in si_pmu_openloop_cal_43012()
8029 si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG1, ~0, pll_reg); in si_pmu_openloop_cal_43012()
8033 si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG1, ~0, pll_reg); in si_pmu_openloop_cal_43012()
8038 dco_code = ((dco_code & 0x0FFF0000) >> 16); in si_pmu_openloop_cal_43012()
8064 si_pmu_pllctrlreg_update(sih, osh, pmu, xtal, 0, in si_pmu_openloop_cal_43012()
8071 si_pmu_pll_on_43012(sih, osh, pmu, 0); in si_pmu_openloop_cal_43012()
8077 pll_reg = si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG3, 0, 0); in si_pmu_openloop_cal_43012()
8078 y3 = (pll_reg >> 16) & 0xFFF; in si_pmu_openloop_cal_43012()
8085 0x0FFF0000, (final_dco_code << 16)); in si_pmu_openloop_cal_43012()
8089 si_pmu_pllcontrol(sih, PMU_PLL_CTRL_REG3, 0x00004000, (1<<14)); in si_pmu_openloop_cal_43012()
8097 W_REG(osh, &pmu->res_updn_timer, 0x01800180); in si_pmu_openloop_cal_43012()
8137 if (xtalfreq == 0) in si_pmu_slow_clk_reinit()
8154 si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_PAREF, 0x0c); in BCMATTACHFN()
8187 pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_pmu_waitforclk_on_backplane()
8205 * Measures the ALP clock frequency in KHz. Returns 0 if not possible.
8212 uint32 pmustat_lpo = 0; in BCMATTACHFN()
8217 return 0; in BCMATTACHFN()
8224 pmu = si_setcore(sih, PMU_CORE_ID, 0); in BCMATTACHFN()
8251 W_REG(osh, &pmu->pmu_xtalfreq, 0); in BCMATTACHFN()
8259 alp_khz = 0; in BCMATTACHFN()
8271 uint32 min_mask = 0, max_mask = 0; in si_pmu_res_minmax_update()
8281 pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_pmu_res_minmax_update()
8289 max_mask = 0; /* Only care about min_mask for now */ in si_pmu_res_minmax_update()
8306 max_mask = 0; /* Don't need to update max */ in si_pmu_res_minmax_update()
8396 uint32 buf_size = 0; in BCMATTACHFN()
8397 uint32 pmu_size = 0; in BCMATTACHFN()
8401 return 0; in BCMATTACHFN()
8427 /* cnt indicates how many registers, tag_id 0 will say these are address/value */ in BCMATTACHFN()
8436 if ((PMUREV(sih->pmurev) > 27) && ARRAYSIZE(pmuregsdump) != 0) { in BCMATTACHFN()
8440 if (ARRAYSIZE(pmuregsdump_mac_res1) != 0 && rsrc_cnt > 1) { in BCMATTACHFN()
8444 if (ARRAYSIZE(pmuregsdump_mac_res2) != 0 && rsrc_cnt > 2) { in BCMATTACHFN()
8448 if (ARRAYSIZE(pmuregsdump_pmu_int1) != 0 && in BCMATTACHFN()
8474 uint32 pmu_totalsize = 0; in BCMPOSTTRAPFN()
8479 return 0; in BCMPOSTTRAPFN()
8484 pmu = si_setcore(sih, PMU_CORE_ID, 0); in BCMPOSTTRAPFN()
8496 for (i = 0; i < cnt; i++) { in BCMPOSTTRAPFN()
8506 for (i = 0; i < cnt; i++) { in BCMPOSTTRAPFN()
8507 *p32++ = si_pmu_pllcontrol(sih, i, 0, 0); in BCMPOSTTRAPFN()
8514 for (i = 0; i < cnt; i++) { in BCMPOSTTRAPFN()
8515 *p32++ = si_pmu_vreg_control(sih, i, 0, 0); in BCMPOSTTRAPFN()
8521 for (i = 0; i < cnt; i++) { in BCMPOSTTRAPFN()
8522 *p32++ = si_pmu_chipcontrol(sih, i, 0, 0); in BCMPOSTTRAPFN()
8527 *p32++ = (ARRAYSIZE(chipc_regs_to_dump) << 16 | 0); in BCMPOSTTRAPFN()
8528 for (i = 0; i < ARRAYSIZE(chipc_regs_to_dump); i++) { in BCMPOSTTRAPFN()
8538 for (i = 0; i < ARRAYSIZE(pmuregsdump); i++) { in BCMPOSTTRAPFN()
8547 for (i = 0; i < ARRAYSIZE(pmuregsdump_mac_res1); i++) { in BCMPOSTTRAPFN()
8557 for (i = 0; i < ARRAYSIZE(pmuregsdump_mac_res2); i++) { in BCMPOSTTRAPFN()
8568 for (i = 0; i < ARRAYSIZE(pmuregsdump_pmu_int1); i++) { in BCMPOSTTRAPFN()
8606 pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_pmu_min_res_set()
8639 (up == TRUE) ? PMU_28NM_VREG6_BTLDO3P3_PU : 0x00); in si_pmu_bt_ldo_pu()
8645 uint32 bt_or_wl = 0u; in si_pmu_ldo3p3_soft_start_wl_get()
8683 if (bt_or_wl == 0) { in si_pmu_soft_start_params()
8696 ASSERT(0); in si_pmu_soft_start_params()
8704 uint en_reg = 0, val_reg = 0; in si_pmu_ldo3p3_soft_start_get()
8705 uint32 en_shift = 0, en_mask = 0, en_val = 0, val_shift = 0, val_mask = 0; in si_pmu_ldo3p3_soft_start_get()
8713 soft_start_en = (si_pmu_vreg_control(sih, en_reg, 0, 0) >> en_shift); in si_pmu_ldo3p3_soft_start_get()
8715 if (en_val == 0u) { in si_pmu_ldo3p3_soft_start_get()
8719 slew_rate = (si_pmu_vreg_control(sih, val_reg, 0, 0) >> val_shift); in si_pmu_ldo3p3_soft_start_get()
8730 uint32 bt_or_wl = 0u; in si_pmu_ldo3p3_soft_start_wl_set()
8742 uint en_reg = 0, val_reg = 0; in si_pmu_ldo3p3_soft_start_set()
8743 uint32 en_shift = 0, en_mask = 0, en_val = 0, val_shift = 0, val_mask = 0; in si_pmu_ldo3p3_soft_start_set()
8746 uint32 dis_val = en_val ? 0u : 1u; in si_pmu_ldo3p3_soft_start_set()
8752 if (slew_rate != (uint32)(~0u)) { in si_pmu_ldo3p3_soft_start_set()
8769 /* Slew rate value of 0xFFFF is used as a special value in si_pmu_ldo3p3_soft_start_set()
8777 si_pmu_vreg_control(sih, val_reg, (val_mask << val_shift), 0u); in si_pmu_ldo3p3_soft_start_set()
8789 uint32 min_mask = 0; in si_pmu_min_res_ldo3p3_set()
8790 uint coreidx = si_findcoreidx(sih, GCI_CORE_ID, 0); in si_pmu_min_res_ldo3p3_set()
8798 BCM_MASK32(23, 0), 0x9E9F9F); in si_pmu_min_res_ldo3p3_set()
8801 BCM_MASK32(23, 0), 0x9E9F97); in si_pmu_min_res_ldo3p3_set()
8828 uint32 min_mask = 0; in si_pmu_min_res_otp_pu_set()
8865 wakebit = 0; in BCMPOSTTRAPFN()
8866 ASSERT(0); in BCMPOSTTRAPFN()
8879 pmu = si_setcore(sih, PMU_CORE_ID, 0); in hnd_pmu_clr_int_sts_req_active()
8902 pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_pmu_set_min_res_mask()
8919 return (PMU_REG(sih, core_cap_ext, 0, 0) & PCAP_EXT_USE_MUXED_ILP_CLK_MASK) ? TRUE : FALSE; in si_pmu_cap_fast_lpo()
8934 0); in si_pmu_fast_lpo_disable()
8960 0); in si_pmu_dmn1_perst_wakeup()
8969 * FALSE - returns 0 if xtal programming is same as pllctrl6 register else retruns value of
8978 if (armclk == 0 || xtal == 0) { in si_pmu_pll6val_armclk_calc()
8981 return 0; in si_pmu_pll6val_armclk_calc()
8992 PMU_MSG(("si_pmu_pll6val_armclk_calc, armclk %d, xtal %d, q %d, r 0x%8x, pll6val 0x%8x\n", in si_pmu_pll6val_armclk_calc()
9001 return 0; in si_pmu_pll6val_armclk_calc()
9014 xtal_bias_adj 0xFF 0x1A in BCMATTACHFN()
9015 xtal_coresize_nmos 0x3f 0x3f in BCMATTACHFN()
9016 xtal_coresize_pmos 0x3f 0x3f in BCMATTACHFN()
9017 xtal_sel_bias_res 0x2 0x6 in BCMATTACHFN()
9018 xt_res_bypass 0x0 0x1 in BCMATTACHFN()
9052 xtal_bias_adj 0xFF 0x1A in BCMATTACHFN()
9053 xtal_coresize_nmos 0x3f 0x3f in BCMATTACHFN()
9054 xtal_coresize_pmos 0x3f 0x3f in BCMATTACHFN()
9055 xtal_sel_bias_res 0x2 0x6 in BCMATTACHFN()
9056 xt_res_bypass 0x0 0x1 in BCMATTACHFN()
9086 * xtal_bias_adj 0xFF 0x1A
9087 * xtal_coresize_nmos 0x3f 0x3f
9088 * xtal_coresize_pmos 0x3f 0x3f
9089 * xtal_sel_bias_res 0x2 0x2
9090 * xt_res_bypass 0x0 0x2
9098 uint8 xtal_bias_adj_otp = 0, xtal_bias_cal_otp_done = 0; in BCMATTACHFN()
9107 * register from OTP otherwise write the default value of 0x1a. in BCMATTACHFN()
9110 xtal_bias_adj = xtal_bias_cal_otp_done != 0 ? (xtal_bias_adj << 6) : in BCMATTACHFN()
9140 uint8 xtal_bias_adj = 0, xtal_bias_cal_otp_done = 0; in BCMATTACHFN()
9149 * '0' for xtal_bias_cal_otp_done. in BCMATTACHFN()
9190 ASSERT(0); in BCMATTACHFN()
9212 ASSERT(0); in BCMATTACHFN()
9260 W_REG(osh, &pmu->pmu_statstimer_N, 0); in si_pmustatstimer_update()
9273 pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_pmustatstimer_int_enable()
9295 pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_pmustatstimer_int_disable()
9320 pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_pmustatstimer_init()
9330 for (i = 0; i < max_stats_timer_num; i++) { in si_pmustatstimer_init()
9355 pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_pmustatstimer_dump()
9378 PMU_ERROR(("\tpmucapabilities 0x%8x, core_cap_ext 0x%8x, AlpPeriod 0x%8x, ILPPeriod 0x%8x, " in si_pmustatstimer_dump()
9379 "pmuintmask0 0x%8x, pmuintstatus 0x%8x, pmurev %d\n", in si_pmustatstimer_dump()
9383 for (i = 0; i < max_stats_timer_num; i++) { in si_pmustatstimer_dump()
9387 PMU_ERROR(("\t Timer %d : control 0x%8x, %d\n", in si_pmustatstimer_dump()
9405 pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_pmustatstimer_start()
9430 pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_pmustatstimer_stop()
9455 pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_pmustatstimer_clear()
9462 W_REG(osh, &pmu->pmu_statstimer_N, 0); in si_pmustatstimer_clear()
9482 pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_pmustatstimer_clear_overflow()
9491 for (i = 0; i < max_stats_timer_num; i++) { in si_pmustatstimer_clear_overflow()
9494 if (timerN == 0xFFFFFFFF) { in si_pmustatstimer_clear_overflow()
9515 pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_pmustatstimer_read()
9540 pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_pmustatstimer_cfg_src_num()
9563 pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_pmustatstimer_cfg_cnt_mode()
9644 uint32 core_cap_ext = PMU_REG(sih, core_cap_ext, 0, 0); in BCMPOSTTRAPFN()
9659 uint32 core_cap_ext = PMU_REG(sih, core_cap_ext, 0, 0); in BCMPOSTTRAPFN()
9683 if (core_idx == 0) { in si_pmu_mem_pwr_off()
9689 0); in si_pmu_mem_pwr_off()
9703 0xFFFFFFFF, XTAL_LQ_SETTING_4387); in si_pmu_mem_pwr_off()
9710 0); in si_pmu_mem_pwr_off()
9726 0); in si_pmu_mem_pwr_off()
9773 0xFFFFFFFF, XTAL_HQ_SETTING_4387); in BCMPOSTTRAPFN()
9796 si_pmu_chipcontrol(sih, PMU_CHIPCTL2, PMU_CC2_CB2WL_INTR_PWRREQ_EN, 0); in BCMPOSTTRAPFN()
9797 si_pmu_chipcontrol(sih, PMU_CHIPCTL6, PMU_CC6_ENABLE_DMN1_WAKEUP, 0); in BCMPOSTTRAPFN()
9818 pmu = si_setcore(sih, PMU_CORE_ID, 0); in BCMPOSTTRAPFN()
9824 W_REG(osh, &pmu->pmuintmask0, 0); in BCMPOSTTRAPFN()
9830 W_REG(osh, &pmu->pmuintmask1, 0); in BCMPOSTTRAPFN()
9845 if (PMU_REG(sih, res_state, 0, 0) & PMURES_BIT(RES4387_PWRSW_MAIN)) { in si_pmu_res_state_pwrsw_main_wait()
9846 SPINWAIT((PMU_REG(sih, res_state, 0, 0) & in si_pmu_res_state_pwrsw_main_wait()
9850 ret = (PMU_REG(sih, res_state, 0, 0) & PMURES_BIT(RES4387_PWRSW_MAIN)) ? in si_pmu_res_state_pwrsw_main_wait()
9886 pmuregs_t *pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_pmu_reg_on_war_ext_wake_perst_set()
9892 * ExtWakeMask0 (0x760) register in si_pmu_reg_on_war_ext_wake_perst_set()
9898 * be up during wake-up in ExtWakeReqMask0 (0x770) register in si_pmu_reg_on_war_ext_wake_perst_set()
9900 W_REG(osh, &pmu->extwakereqmask[0], REG_ON_WAR_PMU_EXT_WAKE_REQ_MASK0_VAL); in si_pmu_reg_on_war_ext_wake_perst_set()
9909 uint32 val = 0; in si_pmu_reg_on_war_ext_wake_perst_clear()
9911 pmuregs_t *pmu = si_setcore(sih, PMU_CORE_ID, 0); in si_pmu_reg_on_war_ext_wake_perst_clear()
9915 /* clear all set bits in ExtWakeupStatus (0x744) register */ in si_pmu_reg_on_war_ext_wake_perst_clear()
9927 SPINWAIT(!(PMU_REG(sih, res_state, 0, 0) & PMURES_BIT(rsrc)), PMU_MAX_TRANSITION_DLY); in si_pmu_res_state_wait()
9928 ASSERT(PMU_REG(sih, res_state, 0, 0) & PMURES_BIT(rsrc)); in si_pmu_res_state_wait()