354 	uint		clkstate;		/* State of sd and backplane clock(s) */  member
1376 		if (bus->clkstate == CLK_NONE) {  in dhdsdio_clk_kso_iovar()
1490 		if (bus->clkstate == CLK_NONE) {  in dhdsdio_clk_devsleep_iovar()
1627 		bus->clkstate = (on ? CLK_AVAIL : CLK_SDONLY);  in dhdsdio_htclk()
1639 		bus->clkstate = (on ? CLK_AVAIL : CLK_SDONLY);  in dhdsdio_htclk()
1692 			bus->clkstate = CLK_PENDING;  in dhdsdio_htclk()
1697 			if (bus->clkstate == CLK_PENDING) {  in dhdsdio_htclk()
1723 		bus->clkstate = CLK_AVAIL;  in dhdsdio_htclk()
1751 		if (bus->clkstate == CLK_PENDING) {  in dhdsdio_htclk()
1758 		bus->clkstate = CLK_SDONLY;  in dhdsdio_htclk()
1824 		bus->clkstate = CLK_SDONLY;  in dhdsdio_sdclk()
1852 		bus->clkstate = CLK_NONE;  in dhdsdio_sdclk()
1865 	uint oldstate = bus->clkstate;  in dhdsdio_clkctl()
1871 	if (bus->clkstate == target) {  in dhdsdio_clkctl()
1885 		if (bus->clkstate == CLK_NONE)  in dhdsdio_clkctl()
1921 		if (bus->clkstate == CLK_NONE)  in dhdsdio_clkctl()
1923 		else if (bus->clkstate == CLK_AVAIL)  in dhdsdio_clkctl()
1927 			           bus->clkstate, target));  in dhdsdio_clkctl()
1955 		if (bus->clkstate == CLK_AVAIL)  in dhdsdio_clkctl()
1967 	DHD_INFO(("dhdsdio_clkctl: %d -> %d\n", oldstate, bus->clkstate));  in dhdsdio_clkctl()
2334 	    (bus->clkstate != CLK_AVAIL)) {  in dhd_bus_txdata()
3213 					__FUNCTION__, bus->tx_max, bus->tx_seq, bus->clkstate));  in dhd_bus_txctl()
3702 	            bus->clkstate, bus->activity, bus->idletime, bus->idlecount, bus->sleeping);  in dhd_bus_dump()
5929 	if (bus->clkstate != CLK_AVAIL) {  in dhd_bus_init()
5930 		DHD_ERROR(("%s: clock state is wrong. state = %d\n", __FUNCTION__, bus->clkstate));  in dhd_bus_init()
6865 		if (TXCTLOK(bus) && bus->ctrl_frame_stat && (bus->clkstate == CLK_AVAIL)) {  in dhdsdio_readframes()
6867 		} else if (bus->dotxinrx && (bus->clkstate == CLK_AVAIL) &&  in dhdsdio_readframes()
7728 	if (!SLPAUTO_ENAB(bus) && (bus->clkstate == CLK_PENDING)) {  in dhdsdio_dpc()
7770 			bus->clkstate = CLK_AVAIL;  in dhdsdio_dpc()
7780 	if (bus->clkstate != CLK_AVAIL)  in dhdsdio_dpc()
8013 	if (TXCTLOK(bus) && bus->ctrl_frame_stat && (bus->clkstate == CLK_AVAIL))  in dhdsdio_dpc()
8016 	else if (DATAOK(bus) && strlen(bus->cons_cmd) && (bus->clkstate == CLK_AVAIL) &&  in dhdsdio_dpc()
8023 	else if ((bus->clkstate == CLK_AVAIL) && !bus->fcstate &&  in dhdsdio_dpc()
8064 	} else if (bus->clkstate == CLK_PENDING) {  in dhdsdio_dpc()
8080 	if ((bus->idletime == DHD_IDLE_IMMEDIATE) && (bus->clkstate != CLK_PENDING) &&  in dhdsdio_dpc()
8844 	if ((bus->idletime != 0) && (bus->clkstate == CLK_AVAIL) &&  in dhd_bus_watchdog()
9707 	bus->clkstate = CLK_SDONLY;  in dhdsdio_probe_init()