Lines Matching defs:dhd_bus
278 typedef struct dhd_bus { struct
279 dhd_pub_t *dhd;
281 bcmsdh_info_t *sdh; /* Handle for BCMSDH calls */
282 si_t *sih; /* Handle for SI calls */
283 char *vars; /* Variables (from CIS and/or other) */
284 uint varsz; /* Size of variables buffer */
285 uint32 sbaddr; /* Current SB window pointer (-1, invalid) */
287 sdpcmd_regs_t *regs; /* Registers for SDIO core */
288 uint sdpcmrev; /* SDIO core revision */
289 uint armrev; /* CPU core revision */
290 uint ramrev; /* SOCRAM core revision */
291 uint32 ramsize; /* Size of RAM in SOCRAM (bytes) */
292 uint32 orig_ramsize; /* Size of RAM in SOCRAM (bytes) */
293 uint32 srmemsize; /* Size of SRMEM */
295 uint32 bus; /* gSPI or SDIO bus */
296 uint32 bus_num; /* bus number */
297 uint32 slot_num; /* slot ID */
298 uint32 hostintmask; /* Copy of Host Interrupt Mask */
299 uint32 intstatus; /* Intstatus bits (events) pending */
300 bool dpc_sched; /* Indicates DPC schedule (intrpt rcvd) */
301 bool fcstate; /* State of dongle flow-control */
303 uint16 cl_devid; /* cached devid for dhdsdio_probe_attach() */
304 char *fw_path; /* module_param: path to firmware image */
305 char *nv_path; /* module_param: path to nvram vars file */
307 uint blocksize; /* Block size of SDIO transfers */
308 uint roundup; /* Max roundup limit */
310 struct pktq txq; /* Queue length used for flow-control */
311 uint8 flowcontrol; /* per prio flow control bitmask */
312 uint8 tx_seq; /* Transmit sequence number (next) */
313 uint8 tx_max; /* Maximum transmit sequence allowed */
316 uint8 *hdrbufp;
318 uint8 hdrbuf[MAX_HDR_READ + DHD_SDALIGN];
320 uint8 *rxhdr; /* Header of current rx frame (in hdrbuf) */
321 uint16 nextlen; /* Next Read Len from last header */
322 uint8 rx_seq; /* Receive sequence number (expected) */
323 bool rxskip; /* Skip receive (awaiting NAK ACK) */
325 void *glomd; /* Packet containing glomming descriptor */
326 void *glom; /* Packet chain for glommed superframe */
327 uint glomerr; /* Glom packet read errors */
329 uint8 *rxbuf; /* Buffer for receiving control packets */
330 uint rxblen; /* Allocated length of rxbuf */
331 uint8 *rxctl; /* Aligned pointer into rxbuf */
332 uint8 *databuf; /* Buffer for receiving big glom packet */
333 uint8 *dataptr; /* Aligned pointer into databuf */
334 uint rxlen; /* Length of valid data in buffer */
336 uint8 sdpcm_ver; /* Bus protocol reported by dongle */
338 bool intr; /* Use interrupts */
339 bool poll; /* Use polling */
340 bool ipend; /* Device interrupt is pending */
341 bool intdis; /* Interrupts disabled by isr */
342 uint intrcount; /* Count of device interrupt callbacks */
343 uint lastintrs; /* Count as of last watchdog timer */
344 uint spurious; /* Count of spurious interrupts */
345 uint pollrate; /* Ticks between device polls */
346 uint polltick; /* Tick counter */
347 uint pollcnt; /* Count of active polls */
349 dhd_console_t console; /* Console output polling support */
350 uint console_addr; /* Console address from shared struct */
352 uint regfails; /* Count of R_REG/W_REG failures */
354 uint clkstate; /* State of sd and backplane clock(s) */
355 bool activity; /* Activity flag for clock down */
356 int32 idletime; /* Control for activity timeout */
357 int32 idlecount; /* Activity timeout counter */
358 int32 idleclock; /* How to set bus driver when idle */
359 int32 sd_divisor; /* Speed control to bus driver */
360 int32 sd_mode; /* Mode control to bus driver */
361 int32 sd_rxchain; /* If bcmsdh api accepts PKT chains */
362 bool use_rxchain; /* If dhd should use PKT chains */
363 bool sleeping; /* Is SDIO bus sleeping? */
365 wait_queue_head_t bus_sleep;
367 bool ctrl_wait;
368 wait_queue_head_t ctrl_tx_wait;
369 uint rxflow_mode; /* Rx flow control mode */
370 bool rxflow; /* Is rx flow control on */
371 uint prev_rxlim_hit; /* Is prev rx limit exceeded (per dpc schedule) */
373 bool _nopmu; /* No PMU (FPGA), don't try it */
374 bool clockpoll; /* Force clock polling (no chipactive interrupt) */
376 bool alp_only; /* Don't use HT clock (ALP only) */
378 bool usebufpool;
379 int32 txinrx_thres; /* num of in-queued pkts */
380 int32 dotxinrx; /* tx first in dhdsdio_readframes */
382 bool rxlim_en;
383 uint32 rxlim_addr;
387 bool ext_loop;
388 uint8 loopid;
391 uint pktgen_freq; /* Ticks between bursts */
392 uint pktgen_count; /* Packets to send each burst */
393 uint pktgen_print; /* Bursts between count displays */
394 uint pktgen_total; /* Stop after this many */
395 uint pktgen_minlen; /* Minimum packet data len */
396 uint pktgen_maxlen; /* Maximum packet data len */
397 uint pktgen_mode; /* Configured mode: tx, rx, or echo */
398 uint pktgen_stop; /* Number of tx failures causing stop */
401 uint pktgen_tick; /* Tick counter for bursts */
402 uint pktgen_ptick; /* Burst counter for printing */
403 uint pktgen_sent; /* Number of test packets generated */
404 uint pktgen_rcvd; /* Number of test packets received */
405 uint pktgen_prev_time; /* Time at which previous stats where printed */
406 uint pktgen_prev_sent; /* Number of test packets generated when
409 uint pktgen_prev_rcvd; /* Number of test packets received when
412 uint pktgen_fail; /* Number of failed send attempts */
413 uint16 pktgen_len; /* Length of next packet to send */
416 uint16 pktgen_rcv_state; /* receive state */
417 uint pktgen_rcvd_rcvsession; /* test pkts rcvd per rcv session. */
421 uint tx_sderrs; /* Count of tx attempts with sd errors */
422 uint fcqueued; /* Tx packets that got queued */
423 uint rxrtx; /* Count of rtx requests (NAK to dongle) */
424 uint rx_toolong; /* Receive frames too long to receive */
425 uint rxc_errors; /* SDIO errors when reading control frames */
426 uint rx_hdrfail; /* SDIO errors on header reads */
427 uint rx_badhdr; /* Bad received headers (roosync?) */
428 uint rx_badseq; /* Mismatched rx sequence number */
429 uint fc_rcvd; /* Number of flow-control events received */
430 uint fc_xoff; /* Number which turned on flow-control */
431 uint fc_xon; /* Number which turned off flow-control */
432 uint rxglomfail; /* Failed deglom attempts */
433 uint rxglomframes; /* Number of glom frames (superframes) */
434 uint rxglompkts; /* Number of packets from glom frames */
435 uint f2rxhdrs; /* Number of header reads */
436 uint f2rxdata; /* Number of frame data reads */
437 uint f2txdata; /* Number of f2 frame writes */
438 uint f1regdata; /* Number of f1 register accesses */
439 wake_counts_t wake_counts; /* Wake up counter */
441 bool dwordmode;
444 uint tx_tailpad_chain; /* Number of tail padding by chaining pad_pkt */
445 uint tx_tailpad_pktget; /* Number of tail padding by new PKTGET */
448 uint tx_deferred; /* Tx calls queued while event pending */
450 uint8 *ctrl_frame_buf;
451 uint32 ctrl_frame_len;
452 bool ctrl_frame_stat;
454 uint32 rxint_mode; /* rx interrupt mode */
456 bool remap; /* Contiguous 1MB RAM: 512K socram + 512K devram
460 bool kso;
461 bool _slpauto;
462 bool _oobwakeup;
463 bool _srenab;
464 bool readframes;
465 bool reqbussleep;
466 uint32 resetinstr;
467 uint32 dongle_ram_base;
491 } dhd_bus_t; argument