Lines Matching defs:dhd_bus
268 typedef struct dhd_bus { struct
269 dhd_pub_t *dhd; /**< pointer to per hardware (dongle) unique instance */
271 struct pci_dev *rc_dev; /* pci RC device handle */
272 struct pci_dev *dev; /* pci device handle */
275 void *pcie_dev;
277 dll_t flowring_active_list; /* constructed list of tx flowring queues */
279 uint64 active_list_last_process_ts;
285 uint32 dev_tx_stuck_monitor;
287 uint32 device_tx_stuck_check;
290 si_t *sih; /* Handle for SI calls */
291 char *vars; /* Variables (from CIS and/or other) */
292 uint varsz; /* Size of variables buffer */
293 uint32 sbaddr; /* Current SB window pointer (-1, invalid) */
294 sbpcieregs_t *reg; /* Registers for PCIE core */
296 uint armrev; /* CPU core revision */
297 uint coreid; /* CPU core id */
298 uint ramrev; /* SOCRAM core revision */
299 uint32 ramsize; /* Size of RAM in SOCRAM (bytes) */
300 uint32 orig_ramsize; /* Size of RAM in SOCRAM (bytes) */
301 uint32 srmemsize; /* Size of SRMEM */
303 uint32 bus; /* gSPI or SDIO bus */
304 uint32 bus_num; /* bus number */
305 uint32 slot_num; /* slot ID */
306 uint32 intstatus; /* Intstatus bits (events) pending */
307 bool dpc_sched; /* Indicates DPC schedule (intrpt rcvd) */
308 bool fcstate; /* State of dongle flow-control */
310 uint16 cl_devid; /* cached devid for dhdsdio_probe_attach() */
311 char *fw_path; /* module_param: path to firmware image */
312 char *nv_path; /* module_param: path to nvram vars file */
314 int processed_nvram_params_len; /* Modified len of NVRAM info */
318 char *nvram_params; /* user specified nvram params. */
319 int nvram_params_len;
322 struct pktq txq; /* Queue length used for flow-control */
324 bool intr; /* Use interrupts */
325 bool poll; /* Use polling */
326 bool ipend; /* Device interrupt is pending */
327 bool intdis; /* Interrupts disabled by isr */
328 uint intrcount; /* Count of device interrupt callbacks */
329 uint lastintrs; /* Count as of last watchdog timer */
331 dhd_console_t console; /* Console output polling support */
332 uint console_addr; /* Console address from shared struct */
334 bool alp_only; /* Don't use HT clock (ALP only) */
336 bool remap; /* Contiguous 1MB RAM: 512K socram + 512K devram
340 uint32 resetinstr;
341 uint32 dongle_ram_base;
342 uint32 next_tlv; /* Holds location of next available TLV */
343 ulong shared_addr;
344 pciedev_shared_t *pcie_sh;
345 uint32 dma_rxoffset;
346 volatile char *regs; /* pci device memory va */
347 volatile char *tcm; /* pci device memory va */
348 uint32 bar1_size; /* pci device memory size */
349 uint32 curr_bar1_win; /* current PCIEBar1Window setting */
350 osl_t *osh;
351 uint32 nvram_csm; /* Nvram checksum */
353 bool msi_sim;
354 uchar *msi_sim_addr;
355 dmaaddr_t msi_sim_phys;
356 dhd_dma_buf_t hostfw_buf; /* Host offload firmware buffer */
357 uint32 hostfw_base; /* FW assumed base of host offload mem */
358 uint32 bp_base; /* adjusted bp base of host offload mem */
360 uint16 pollrate;
361 uint16 polltick;
363 volatile uint32 *pcie_mb_intr_addr;
364 volatile uint32 *pcie_mb_intr_2_addr;
365 void *pcie_mb_intr_osh;
366 bool sleep_allowed;
368 wake_counts_t wake_counts;
371 ring_sh_info_t ring_sh[BCMPCIE_COMMON_MSGRINGS + MAX_DHD_TX_FLOWS];
373 uint8 h2d_ring_count;
374 uint8 d2h_ring_count;
375 uint32 ringmem_ptr;
376 uint32 ring_state_ptr;
378 uint32 d2h_dma_scratch_buffer_mem_addr;
380 uint32 h2d_mb_data_ptr_addr;
381 uint32 d2h_mb_data_ptr_addr;
384 uint32 def_intmask;
385 uint32 d2h_mb_mask;
386 uint32 pcie_mailbox_mask;
387 uint32 pcie_mailbox_int;
388 bool ltrsleep_on_unload;
389 uint wait_for_d3_ack;
390 uint16 max_tx_flowrings;
391 uint16 max_submission_rings;
392 uint16 max_completion_rings;
393 uint16 max_cmn_rings;
394 uint32 rw_index_sz;
395 uint32 hwa_db_index_sz;
396 bool db1_for_mb;
398 dhd_timeout_t doorbell_timer;
399 bool device_wake_state;
401 bool oob_enabled;
403 bool irq_registered;
404 bool d2h_intr_method;
405 bool d2h_intr_control;
410 uint8 no_cfg_restore;
412 struct_pcie_register_event pcie_event;
414 bool read_shm_fail;
416 int32 idletime; /* Control for activity timeout */
417 bool rpm_enabled;
419 int32 idlecount; /* Activity timeout counter */
420 int32 bus_wake; /* For wake up the bus */
444 enum dhd_bus_low_power_state bus_low_power_state; argument
446 dhd_frs_trace_t frs_isr_trace[FRS_TRACE_SIZE]; /* frs - flow_ring_status */
447 dhd_frs_trace_t frs_dpc_trace[FRS_TRACE_SIZE]; /* frs - flow_ring_status */
448 uint32 frs_isr_count;
449 uint32 frs_dpc_count;
452 dhd_mmio_trace_t mmio_trace[MAX_MMIO_TRACE_SIZE];
453 uint32 mmio_trace_count;
455 dhd_ds_trace_t ds_trace[MAX_DS_TRACE_SIZE];
456 uint32 ds_trace_count;
457 uint32 hostready_count; /* Number of hostready issued */
459 bool oob_presuspend;
461 dhdpcie_config_save_t saved_config;
462 ulong resume_intr_enable_count;
463 ulong dpc_intr_enable_count;
464 ulong isr_intr_disable_count;
465 ulong suspend_intr_disable_count;
466 ulong dpc_return_busdown_count;
467 ulong non_ours_irq_count;
469 ulong oob_intr_count;
470 ulong oob_intr_enable_count;
471 ulong oob_intr_disable_count;
472 uint64 last_oob_irq_isr_time;
473 uint64 last_oob_irq_thr_time;
474 uint64 last_oob_irq_enable_time;
475 uint64 last_oob_irq_disable_time;
477 uint64 isr_entry_time;
478 uint64 isr_exit_time;
479 uint64 isr_sched_dpc_time;
480 uint64 rpm_sched_dpc_time;
481 uint64 dpc_entry_time;
482 uint64 dpc_exit_time;
483 uint64 resched_dpc_time;
484 uint64 last_d3_inform_time;
485 uint64 last_process_ctrlbuf_time;
486 uint64 last_process_flowring_time;
487 uint64 last_process_txcpl_time;
488 uint64 last_process_rxcpl_time;
489 uint64 last_process_infocpl_time;
490 uint64 last_process_edl_time;
491 uint64 last_suspend_start_time;
492 uint64 last_suspend_end_time;
493 uint64 last_resume_start_time;
494 uint64 last_resume_end_time;
495 uint64 last_non_ours_irq_time;
496 bool hwa_enabled;
497 bool idma_enabled;
498 bool ifrm_enabled;
499 bool dar_enabled;
500 uint32 dmaxfer_complete;
501 uint8 dw_option;
503 bool inb_enabled;
504 uint32 ds_exit_timeout;
505 uint32 host_sleep_exit_timeout;
506 uint wait_for_ds_exit;
507 uint32 inband_dw_assert_cnt; /* # of inband device_wake assert */
508 uint32 inband_dw_deassert_cnt; /* # of inband device_wake deassert */
509 uint32 inband_ds_exit_host_cnt; /* # of DS-EXIT , host initiated */
510 uint32 inband_ds_exit_device_cnt; /* # of DS-EXIT , device initiated */
511 uint32 inband_ds_exit_to_cnt; /* # of DS-EXIT timeout */
512 uint32 inband_host_sleep_exit_to_cnt; /* # of Host_Sleep exit timeout */
513 void *inb_lock; /* Lock to serialize in band device wake activity */
515 uint32 host_active_cnt;
516 bool skip_ds_ack; /* Skip DS-ACK during suspend in progress */
519 bool ds_enabled;
522 bool chk_pm; /* To avoid counting of wake up from Runtime PM */
525 bool calc_ds_exit_latency;
526 bool deep_sleep; /* Indicates deep_sleep set or unset by the DHD IOVAR deep_sleep */
527 uint64 ds_exit_latency;
528 uint64 ds_exit_ts1;
529 uint64 ds_exit_ts2;
531 bool _dar_war;
534 bool gdb_proxy_access_enabled;
536 uint32 gdb_proxy_last_id;
538 bool gdb_proxy_bootloader_mode;
540 uint8 dma_chan;
542 bool cto_enable; /* enable PCIE CTO Prevention and recovery */
543 uint32 cto_threshold; /* PCIE CTO timeout threshold */
544 bool cto_triggered; /* CTO is triggered */
545 bool intr_enabled; /* ready to receive interrupts from dongle */
546 int pwr_req_ref;
547 bool flr_force_fail; /* user intends to simulate flr force fail */
553 uint32 ramtop_addr; /* Dongle address of unused space at top of RAM */
554 uint32 fw_download_addr; /* Dongle address of FW download */
555 uint32 fw_download_len; /* Length in bytes of FW download */
556 uint32 fwsig_download_addr; /* Dongle address of FW signature download */
557 uint32 fwsig_download_len; /* Length in bytes of FW signature download */
558 uint32 fwstat_download_addr; /* Dongle address of FWS status download */
559 uint32 fwstat_download_len; /* Length in bytes of FWS status download */
560 uint32 fw_memmap_download_addr; /* Dongle address of FWS memory-info download */
561 uint32 fw_memmap_download_len; /* Length in bytes of FWS memory-info download */
563 char fwsig_filename[DHD_FILENAME_MAX]; /* Name of FW signature file */
564 char bootloader_filename[DHD_FILENAME_MAX]; /* Name of bootloader image file */
565 uint32 bootloader_addr; /* Dongle address of bootloader download */
566 bool force_bt_quiesce; /* send bt_quiesce command to BT driver. */
567 bool rc_ep_aspm_cap; /* RC and EP ASPM capable */
568 bool rc_ep_l1ss_cap; /* EC and EP L1SS capable */
570 ulong dhd_rte_time_sync_count; /* OSL_SYSUPTIME_US() */
594 } dhd_bus_t; argument