1682 		OSL_PCI_WRITE_CONFIG(osh, i << 2, sizeof(uint32), bus->saved_config.header[i]);  in dhdpcie_config_restore()
1684 	OSL_PCI_WRITE_CONFIG(osh, PCI_CFG_CMD, sizeof(uint32), bus->saved_config.header[1]);  in dhdpcie_config_restore()
1688 			sizeof(uint32), bus->saved_config.pmcsr);  in dhdpcie_config_restore()
1690 	OSL_PCI_WRITE_CONFIG(osh, PCIECFGREG_MSI_CAP, sizeof(uint32), bus->saved_config.msi_cap);  in dhdpcie_config_restore()
1692 			bus->saved_config.msi_addr0);  in dhdpcie_config_restore()
1694 			sizeof(uint32), bus->saved_config.msi_addr1);  in dhdpcie_config_restore()
1696 			sizeof(uint32), bus->saved_config.msi_data);  in dhdpcie_config_restore()
1699 			sizeof(uint32), bus->saved_config.exp_dev_ctrl_stat);  in dhdpcie_config_restore()
1701 			sizeof(uint32), bus->saved_config.exp_dev_ctrl_stat2);  in dhdpcie_config_restore()
1703 			sizeof(uint32), bus->saved_config.exp_link_ctrl_stat);  in dhdpcie_config_restore()
1705 			sizeof(uint32), bus->saved_config.exp_link_ctrl_stat2);  in dhdpcie_config_restore()
1708 			sizeof(uint32), bus->saved_config.l1pm0);  in dhdpcie_config_restore()
1710 			sizeof(uint32), bus->saved_config.l1pm1);  in dhdpcie_config_restore()
1713 			bus->saved_config.bar0_win);  in dhdpcie_config_restore()
1714 	dhdpcie_setbar1win(bus, bus->saved_config.bar1_win);  in dhdpcie_config_restore()
1730 		bus->saved_config.header[i] = OSL_PCI_READ_CONFIG(osh, i << 2, sizeof(uint32));  in dhdpcie_config_save()
1733 	bus->saved_config.pmcsr = OSL_PCI_READ_CONFIG(osh, PCIECFGREG_PM_CSR, sizeof(uint32));  in dhdpcie_config_save()
1735 	bus->saved_config.msi_cap = OSL_PCI_READ_CONFIG(osh, PCIECFGREG_MSI_CAP,  in dhdpcie_config_save()
1737 	bus->saved_config.msi_addr0 = OSL_PCI_READ_CONFIG(osh, PCIECFGREG_MSI_ADDR_L,  in dhdpcie_config_save()
1739 	bus->saved_config.msi_addr1 = OSL_PCI_READ_CONFIG(osh, PCIECFGREG_MSI_ADDR_H,  in dhdpcie_config_save()
1741 	bus->saved_config.msi_data = OSL_PCI_READ_CONFIG(osh, PCIECFGREG_MSI_DATA,  in dhdpcie_config_save()
1744 	bus->saved_config.exp_dev_ctrl_stat = OSL_PCI_READ_CONFIG(osh,  in dhdpcie_config_save()
1746 	bus->saved_config.exp_dev_ctrl_stat2 = OSL_PCI_READ_CONFIG(osh,  in dhdpcie_config_save()
1748 	bus->saved_config.exp_link_ctrl_stat = OSL_PCI_READ_CONFIG(osh,  in dhdpcie_config_save()
1750 	bus->saved_config.exp_link_ctrl_stat2 = OSL_PCI_READ_CONFIG(osh,  in dhdpcie_config_save()
1753 	bus->saved_config.l1pm0 = OSL_PCI_READ_CONFIG(osh, PCIECFGREG_PML1_SUB_CTRL1,  in dhdpcie_config_save()
1755 	bus->saved_config.l1pm1 = OSL_PCI_READ_CONFIG(osh, PCIECFGREG_PML1_SUB_CTRL2,  in dhdpcie_config_save()
1758 	bus->saved_config.bar0_win = OSL_PCI_READ_CONFIG(osh, PCI_BAR0_WIN,  in dhdpcie_config_save()
1760 	bus->saved_config.bar1_win = OSL_PCI_READ_CONFIG(osh, PCI_BAR1_WIN,  in dhdpcie_config_save()