Lines Matching refs:cr4regs_t
17177 cr4regs_t *cr4regs; in dhd_pcie_dump_wrapper_regs()
17199 DHD_ERROR(("reg:0x%x val:0x%x\n", (uint)OFFSETOF(cr4regs_t, corecontrol), val)); in dhd_pcie_dump_wrapper_regs()
17202 (uint)OFFSETOF(cr4regs_t, corecapabilities), val)); in dhd_pcie_dump_wrapper_regs()
17204 DHD_ERROR(("reg:0x%x val:0x%x\n", (uint)OFFSETOF(cr4regs_t, corestatus), val)); in dhd_pcie_dump_wrapper_regs()
17206 DHD_ERROR(("reg:0x%x val:0x%x\n", (uint)OFFSETOF(cr4regs_t, nmiisrst), val)); in dhd_pcie_dump_wrapper_regs()
17208 DHD_ERROR(("reg:0x%x val:0x%x\n", (uint)OFFSETOF(cr4regs_t, nmimask), val)); in dhd_pcie_dump_wrapper_regs()
17210 DHD_ERROR(("reg:0x%x val:0x%x\n", (uint)OFFSETOF(cr4regs_t, isrmask), val)); in dhd_pcie_dump_wrapper_regs()
17212 DHD_ERROR(("reg:0x%x val:0x%x\n", (uint)OFFSETOF(cr4regs_t, swintreg), val)); in dhd_pcie_dump_wrapper_regs()
17214 DHD_ERROR(("reg:0x%x val:0x%x\n", (uint)OFFSETOF(cr4regs_t, intstatus), val)); in dhd_pcie_dump_wrapper_regs()
17216 DHD_ERROR(("reg:0x%x val:0x%x\n", (uint)OFFSETOF(cr4regs_t, cyclecnt), val)); in dhd_pcie_dump_wrapper_regs()
17218 DHD_ERROR(("reg:0x%x val:0x%x\n", (uint)OFFSETOF(cr4regs_t, inttimer), val)); in dhd_pcie_dump_wrapper_regs()
17220 DHD_ERROR(("reg:0x%x val:0x%x\n", (uint)OFFSETOF(cr4regs_t, clk_ctl_st), val)); in dhd_pcie_dump_wrapper_regs()
17222 DHD_ERROR(("reg:0x%x val:0x%x\n", (uint)OFFSETOF(cr4regs_t, powerctl), val)); in dhd_pcie_dump_wrapper_regs()