Lines Matching refs:cr4_regs
1972 volatile uint32 *cr4_regs; in dhdpcie_bus_mpu_disable() local
1985 cr4_regs = si_setcore(bus->sih, ARMCR4_CORE_ID, 0); in dhdpcie_bus_mpu_disable()
1986 if (cr4_regs == NULL) { in dhdpcie_bus_mpu_disable()
1990 if (R_REG(bus->osh, cr4_regs + ARMCR4REG_CORECAP) & ACC_MPU_MASK) { in dhdpcie_bus_mpu_disable()
1992 W_REG(bus->osh, cr4_regs + ARMCR4REG_MPUCTRL, 0); in dhdpcie_bus_mpu_disable()
10290 volatile uint32 *cr4_regs; in dhdpcie_bus_download_state() local
10351 cr4_regs = si_setcore(bus->sih, ARMCR4_CORE_ID, 0); in dhdpcie_bus_download_state()
10353 if (cr4_regs == NULL && !(si_setcore(bus->sih, ARM7S_CORE_ID, 0)) && in dhdpcie_bus_download_state()
10372 } else if (cr4_regs == NULL) { /* no CR4 present on chip */ in dhdpcie_bus_download_state()
10405 W_REG(bus->pcie_mb_intr_osh, cr4_regs + ARMCR4REG_BANKIDX, 5); in dhdpcie_bus_download_state()
10406 W_REG(bus->pcie_mb_intr_osh, cr4_regs + ARMCR4REG_BANKPDA, 0); in dhdpcie_bus_download_state()
10407 W_REG(bus->pcie_mb_intr_osh, cr4_regs + ARMCR4REG_BANKIDX, 7); in dhdpcie_bus_download_state()
10408 W_REG(bus->pcie_mb_intr_osh, cr4_regs + ARMCR4REG_BANKPDA, 0); in dhdpcie_bus_download_state()