Lines Matching refs:u
2869 OFFSETOF(sbpcieregs_t, u.pcie2.ltr_state), ~0, 0); in dhdpcie_bus_release_dongle()
3649 #define PCIE_HYBRIDFW_TYPE_DNGL 0u
10142 OFFSETOF(sbpcieregs_t, u.pcie2.clk_ctl_st), CCS_FORCEALP, CCS_FORCEALP); in dhdpcie_force_alp()
10145 OFFSETOF(sbpcieregs_t, u.pcie2.clk_ctl_st), CCS_FORCEALP, 0); in dhdpcie_force_alp()
17618 (uint)OFFSETOF(sbpcieregs_t, u.pcie2.err_hdr_logreg1), in dhd_pcie_debug_info_dump()
17620 OFFSETOF(sbpcieregs_t, u.pcie2.err_hdr_logreg1), 0, 0), in dhd_pcie_debug_info_dump()
17621 (uint)OFFSETOF(sbpcieregs_t, u.pcie2.err_hdr_logreg2), in dhd_pcie_debug_info_dump()
17623 OFFSETOF(sbpcieregs_t, u.pcie2.err_hdr_logreg2), 0, 0), in dhd_pcie_debug_info_dump()
17624 (uint)OFFSETOF(sbpcieregs_t, u.pcie2.err_hdr_logreg3), in dhd_pcie_debug_info_dump()
17626 OFFSETOF(sbpcieregs_t, u.pcie2.err_hdr_logreg3), 0, 0), in dhd_pcie_debug_info_dump()
17627 (uint)OFFSETOF(sbpcieregs_t, u.pcie2.err_hdr_logreg4), in dhd_pcie_debug_info_dump()
17629 OFFSETOF(sbpcieregs_t, u.pcie2.err_hdr_logreg4), 0, 0))); in dhd_pcie_debug_info_dump()
17631 (uint)OFFSETOF(sbpcieregs_t, u.pcie2.err_code_logreg), in dhd_pcie_debug_info_dump()
17633 OFFSETOF(sbpcieregs_t, u.pcie2.err_code_logreg), 0, 0))); in dhd_pcie_debug_info_dump()