Lines Matching defs:sdioh_info
130 struct sdioh_info { struct
131 uint cfg_bar; /* pci cfg address for bar */
132 uint32 caps; /* cached value of capabilities reg */
133 uint32 curr_caps; /* max current capabilities reg */
135 osl_t *osh; /* osh handler */
136 volatile char *mem_space; /* pci device memory va */
137 uint lockcount; /* nest count of sdstd_lock() calls */
138 bool client_intr_enabled; /* interrupt connnected flag */
139 bool intr_handler_valid; /* client driver interrupt handler valid */
140 sdioh_cb_fn_t intr_handler; /* registered interrupt handler */
141 void *intr_handler_arg; /* argument to call interrupt handler */
142 bool initialized; /* card initialized */
143 uint target_dev; /* Target device ID */
144 uint16 intmask; /* Current active interrupts */
145 void *sdos_info; /* Pointer to per-OS private data */
146 void *bcmsdh; /* handler to upper layer stack (bcmsdh) */
148 uint32 controller_type; /* Host controller type */
149 uint8 version; /* Host Controller Spec Compliance Version */
150 uint irq; /* Client irq */
151 int intrcount; /* Client interrupts */
152 int local_intrcount; /* Controller interrupts */
153 bool host_init_done; /* Controller initted */
154 bool card_init_done; /* Client SDIO interface initted */
155 bool polled_mode; /* polling for command completion */
157 bool sd_blockmode; /* sd_blockmode == FALSE => 64 Byte Cmd 53s. */
159 bool use_client_ints; /* If this is false, make sure to restore */
161 int adapter_slot; /* Maybe dealing with multiple slots/controllers */
162 int sd_mode; /* SD1/SD4/SPI */
163 int client_block_size[SDIOD_MAX_IOFUNCS]; /* Blocksize */
164 uint32 data_xfer_count; /* Current transfer */
165 uint16 card_rca; /* Current Address */
166 int8 sd_dma_mode; /* DMA Mode (PIO, SDMA, ... ADMA2) on CMD53 */
167 uint8 num_funcs; /* Supported funcs on client */
168 uint32 com_cis_ptr;
169 uint32 func_cis_ptr[SDIOD_MAX_IOFUNCS];
170 void *dma_buf; /* DMA Buffer virtual address */
171 dmaaddr_t dma_phys; /* DMA Buffer physical address */
172 void *adma2_dscr_buf; /* ADMA2 Descriptor Buffer virtual address */
173 dmaaddr_t adma2_dscr_phys; /* ADMA2 Descriptor Buffer physical address */
176 void *dma_start_buf;
177 dmaaddr_t dma_start_phys;
178 uint alloced_dma_size;
179 void *adma2_dscr_start_buf;
180 dmaaddr_t adma2_dscr_start_phys;
181 uint alloced_adma2_dscr_size;
183 int r_cnt; /* rx count */
184 int t_cnt; /* tx_count */
185 bool got_hcint; /* local interrupt flag */
186 uint16 last_intrstatus; /* to cache intrstatus */
187 int host_UHSISupported; /* whether UHSI is supported for HC. */
188 int card_UHSI_voltage_Supported; /* whether UHSI is supported for
191 int global_UHSI_Supp; /* type of UHSI support in both host and card.
196 volatile int sd3_dat_state; /* data transfer state used for retuning check */
197 volatile int sd3_tun_state; /* tuning state used for retuning check */
198 bool sd3_tuning_reqd; /* tuning requirement parameter */
199 bool sd3_tuning_disable; /* tuning disable due to bus sleeping */
200 uint32 caps3; /* cached value of 32 MSbits capabilities reg (SDIO 3.0) */
202 glom_buf_t glom_info; /* pkt information used for glomming */
203 uint txglom_mode; /* Txglom mode: 0 - copy, 1 - multi-descriptor */