583 	sdstd_or_reg16(sd, SD_ClockCntrl, 0x4);  in sdstd_turn_on_clock()
589 	sdstd_wreg16(sd, SD_ClockCntrl, sdstd_rreg16(sd, SD_ClockCntrl) & ~((uint16)0x4));  in sdstd_turn_off_clock()
817 			sdstd_wreg16(si, SD_ClockCntrl,  in sdioh_iovar_op()
818 			             sdstd_rreg16(si, SD_ClockCntrl) & ~((uint16)0x4));  in sdioh_iovar_op()
2758 	sdstd_wreg16(sd, SD_ClockCntrl,  in sdstd_3_set_highspeed_uhsi_mode()
2759 		sdstd_rreg16(sd, SD_ClockCntrl) & ~((uint16)0x4));  in sdstd_3_set_highspeed_uhsi_mode()
3092 	sdstd_wreg16(sd, SD_ClockCntrl,  in sdstd_3_sigvoltswitch_proc()
3093 	             sdstd_rreg16(sd, SD_ClockCntrl) & ~((uint16)0x4));  in sdstd_3_sigvoltswitch_proc()
3119 	val1 = sdstd_rreg16(sd, SD_ClockCntrl);  in sdstd_3_sigvoltswitch_proc()
3120 	sdstd_wreg16(sd, SD_ClockCntrl, val1 | 0x4);  in sdstd_3_sigvoltswitch_proc()
3359 	reg16 = sdstd_rreg16(sd, SD_ClockCntrl);  in print_regs()
3481 	sdstd_wreg16(sd, SD_ClockCntrl,  in sdstd_start_clock()
3482 	             sdstd_rreg16(sd, SD_ClockCntrl) & ~((uint16)0x4)); /*  Disable the HC clock */  in sdstd_start_clock()
3516 	sd_info(("Clock control is 0x%x\n", sdstd_rreg16(sd, SD_ClockCntrl)));  in sdstd_start_clock()
3526 		sdstd_mod_reg16(sd, SD_ClockCntrl, 0xffC0, val1);  in sdstd_start_clock()
3529 		sdstd_mod_reg16(sd, SD_ClockCntrl, 0xff00, divisor);  in sdstd_start_clock()
3569 	sdstd_or_reg16(sd, SD_ClockCntrl, 0x1); /*  Enable the clock */  in sdstd_start_clock()
3572 	rc = (sdstd_rreg16(sd, SD_ClockCntrl) & 2);  in sdstd_start_clock()
3577 		rc = (sdstd_rreg16(sd, SD_ClockCntrl) & 2);  in sdstd_start_clock()
3586 	sdstd_or_reg16(sd, SD_ClockCntrl, 0x4);  in sdstd_start_clock()
3622 	sd_info(("Final Clock control is 0x%x\n", sdstd_rreg16(sd, SD_ClockCntrl)));  in sdstd_start_clock()