Lines Matching +full:mode +full:- +full:xxx
21 * <<Broadcom-WL-IPTag/Open:>>
39 /* XXX Quick NDIS hack */
51 * Upper GPIO 16 - 31 are available on J22
53 * Lower GPIO 0 - 15 are available on J15 (WL_GPIO)
64 uint sd_hiok = TRUE; /* Use hi-speed mode if available? */
65 uint sd_sdmode = SDIOH_MODE_SD4; /* Use SD4 mode by default */
71 /* sd3ClkMode: 0-SDR12 [25MHz]
72 * 1-SDR25 [50MHz]+SHS=1
73 * 2-SDR50 [100MHz]+SSDR50=1
74 * 3-SDR104 [208MHz]+SSDR104=1
75 * 4-DDR50 [50MHz]+SDDR50=1
82 #define SD3CLKMODE_DISABLED (-1)
90 /* depends-on/affects sd3_autoselect_uhsi_max.
114 0x1, /* Driver Strength Type-A */
115 0x0, /* Driver Strength Type-B */
116 0x2, /* Driver Strength Type-C */
117 0x3, /* Driver Strength Type-D */
120 /* depends-on/affects sd_uhsimode.
123 by the user specifically, this var becomes 0. default value: 0. [XXX:TBD: for future]
128 /* (150+10)millisecs total time; so dividing it for per-loop */
172 (sd->version == HOST_CONTR_VER_3) && \
175 (GFIELD(sd->caps3, CAP3_TUNING_SDR50)))))
178 #define NEXT_POW2(n) {n--; n |= n>>1; n |= n>>2; n |= n>>4; n++;}
186 /* XXX: Issues with CMD14 enter/exit sleep
187 * XXX: Temp fix for special CMD14 handling
201 /* XXX Base timeout counter value on 48MHz (2^20 @ 48MHz => 21845us)
269 /* XXX This is a hack to satisfy the -Wmissing-prototypes warning */
275 volatile uint16 data = *(volatile uint16 *)(sd->mem_space + reg); in sdstd_rreg16()
280 /* XXX This is a hack to satisfy the -Wmissing-prototypes warning */
285 *(volatile uint16 *)(sd->mem_space + reg) = (uint16) data; in sdstd_wreg16()
292 volatile uint16 data = *(volatile uint16 *)(sd->mem_space + reg); in sdstd_or_reg16()
295 *(volatile uint16 *)(sd->mem_space + reg) = (uint16)data; in sdstd_or_reg16()
302 volatile uint16 data = *(volatile uint16 *)(sd->mem_space + reg); in sdstd_mod_reg16()
306 *(volatile uint16 *)(sd->mem_space + reg) = (uint16)data; in sdstd_mod_reg16()
313 volatile uint32 data = *(volatile uint32 *)(sd->mem_space + reg); in sdstd_rreg()
320 *(volatile uint32 *)(sd->mem_space + reg) = (uint32)data; in sdstd_wreg()
329 volatile uint32 data = *(volatile uint32 *)(sd->mem_space + reg); in sdstd_or_reg()
331 *(volatile uint32 *)(sd->mem_space + reg) = (volatile uint32)data; in sdstd_or_reg()
336 volatile uint32 data = *(volatile uint32 *)(sd->mem_space + reg); in sdstd_mod_reg()
339 *(volatile uint32 *)(sd->mem_space + reg) = (volatile uint32)data; in sdstd_mod_reg()
348 *(volatile uint8 *)(sd->mem_space + reg) = (uint8)data; in sdstd_wreg8()
354 volatile uint8 data = *(volatile uint8 *)(sd->mem_space + reg); in sdstd_rreg8()
380 sd->osh = osh; in sdioh_attach()
383 MFREE(sd->osh, sd, sizeof(sdioh_info_t)); in sdioh_attach()
386 sd->mem_space = (volatile char *)sdstd_reg_map(osh, (ulong)bar0, SDIOH_REG_WINSZ); in sdioh_attach()
388 sd->irq = irq; in sdioh_attach()
389 if (sd->mem_space == NULL) { in sdioh_attach()
392 MFREE(sd->osh, sd, sizeof(sdioh_info_t)); in sdioh_attach()
395 sd_info(("%s:sd->mem_space = %p\n", __FUNCTION__, sd->mem_space)); in sdioh_attach()
396 sd->intr_handler = NULL; in sdioh_attach()
397 sd->intr_handler_arg = NULL; in sdioh_attach()
398 sd->intr_handler_valid = FALSE; in sdioh_attach()
401 sd->sd_blockmode = TRUE; in sdioh_attach()
402 sd->use_client_ints = TRUE; in sdioh_attach()
403 sd->sd_dma_mode = sd_dma_mode; in sdioh_attach()
405 /* XXX Haven't figured out how to make bytemode work with dma */ in sdioh_attach()
406 if (!sd->sd_blockmode) in sdioh_attach()
407 sd->sd_dma_mode = DMA_MODE_NONE; in sdioh_attach()
415 sd_info(("driver_init failed - Reset RCA and try again\n")); in sdioh_attach()
418 if (sd->mem_space) { in sdioh_attach()
419 sdstd_reg_unmap(osh, (ulong)sd->mem_space, SDIOH_REG_WINSZ); in sdioh_attach()
420 sd->mem_space = NULL; in sdioh_attach()
423 MFREE(sd->osh, sd, sizeof(sdioh_info_t)); in sdioh_attach()
428 /* XXX Needed for NDIS as its OSL checks for correct dma address width in sdioh_attach()
438 sdstd_free_irq(sd->irq, sd); in sdioh_attach()
439 if (sd->mem_space) { in sdioh_attach()
440 sdstd_reg_unmap(osh, (ulong)sd->mem_space, SDIOH_REG_WINSZ); in sdioh_attach()
441 sd->mem_space = NULL; in sdioh_attach()
445 MFREE(sd->osh, sd, sizeof(sdioh_info_t)); in sdioh_attach()
460 if (sd->sd3_tuning_reqd == TRUE) { in sdioh_detach()
462 sd->sd3_tuning_reqd = FALSE; in sdioh_detach()
464 sd->sd3_tuning_disable = FALSE; in sdioh_detach()
465 sd_trace(("%s: freeing irq %d\n", __FUNCTION__, sd->irq)); in sdioh_detach()
466 sdstd_free_irq(sd->irq, sd); in sdioh_detach()
467 if (sd->card_init_done) in sdioh_detach()
469 if (sd->mem_space) { in sdioh_detach()
470 sdstd_reg_unmap(osh, (ulong)sd->mem_space, SDIOH_REG_WINSZ); in sdioh_detach()
471 sd->mem_space = NULL; in sdioh_detach()
475 MFREE(sd->osh, sd, sizeof(sdioh_info_t)); in sdioh_detach()
485 sd->intr_handler = fn; in sdioh_interrupt_register()
486 sd->intr_handler_arg = argh; in sdioh_interrupt_register()
487 sd->intr_handler_valid = TRUE; in sdioh_interrupt_register()
495 sd->intr_handler_valid = FALSE; in sdioh_interrupt_deregister()
496 sd->intr_handler = NULL; in sdioh_interrupt_deregister()
497 sd->intr_handler_arg = NULL; in sdioh_interrupt_deregister()
505 *onoff = sd->client_intr_enabled; in sdioh_interrupt_query()
522 return sd->num_funcs; in sdioh_query_iofnum()
620 /* XXX Copied from dhd, copied from wl; certainly overkill here? */ in sdioh_iovar_op()
627 if (vi->type == IOVT_VOID) in sdioh_iovar_op()
629 else if (vi->type == IOVT_BUFFER) in sdioh_iovar_op()
640 actionid = set ? IOV_SVAL(vi->varid) : IOV_GVAL(vi->varid); in sdioh_iovar_op()
652 int_val = (int32)si->sd_blockmode; in sdioh_iovar_op()
657 si->sd_blockmode = (bool)int_val; in sdioh_iovar_op()
658 /* Haven't figured out how to make non-block mode with DMA */ in sdioh_iovar_op()
659 if (!si->sd_blockmode) in sdioh_iovar_op()
660 si->sd_dma_mode = DMA_MODE_NONE; in sdioh_iovar_op()
693 if ((uint32)int_val > si->num_funcs) { in sdioh_iovar_op()
697 int_val = (int32)si->client_block_size[int_val]; in sdioh_iovar_op()
707 if (func > si->num_funcs) { in sdioh_iovar_op()
712 /* XXX These hardcoded sizes are a hack, remove after proper CIS parsing. */ in sdioh_iovar_op()
735 int_val = (int32)si->sd_dma_mode; in sdioh_iovar_op()
740 si->sd_dma_mode = (char)int_val; in sdioh_iovar_op()
741 sdstd_set_dma_mode(si, si->sd_dma_mode); in sdioh_iovar_op()
745 int_val = (int32)si->use_client_ints; in sdioh_iovar_op()
750 si->use_client_ints = (bool)int_val; in sdioh_iovar_op()
751 if (si->use_client_ints) in sdioh_iovar_op()
752 si->intmask |= CLIENT_INTR; in sdioh_iovar_op()
754 si->intmask &= ~CLIENT_INTR; in sdioh_iovar_op()
859 if (!(si->card_UHSI_voltage_Supported && si->host_UHSISupported)) { in sdioh_iovar_op()
882 sd_err(("%s:Error in setting uhsi to old mode;" in sdioh_iovar_op()
894 si->sd3_tuning_reqd = TRUE; in sdioh_iovar_op()
899 si->sd3_tuning_reqd = FALSE; in sdioh_iovar_op()
903 si->sd3_tuning_reqd = TRUE; in sdioh_iovar_op()
910 int_val = (int32)si->intrcount; in sdioh_iovar_op()
915 int_val = (int32)si->local_intrcount; in sdioh_iovar_op()
921 /* XXX Should copy for alignment reasons */ in sdioh_iovar_op()
924 if (sd_ptr->offset < SD_SysAddr || sd_ptr->offset > SD3_WL_BT_reset_register) { in sdioh_iovar_op()
925 sd_err(("%s: bad offset 0x%x\n", __FUNCTION__, sd_ptr->offset)); in sdioh_iovar_op()
931 (sd_ptr->offset & 1) ? 8 : ((sd_ptr->offset & 2) ? 16 : 32), in sdioh_iovar_op()
932 sd_ptr->offset)); in sdioh_iovar_op()
933 if (sd_ptr->offset & 1) in sdioh_iovar_op()
934 int_val = sdstd_rreg8(si, sd_ptr->offset); in sdioh_iovar_op()
935 else if (sd_ptr->offset & 2) in sdioh_iovar_op()
936 int_val = sdstd_rreg16(si, sd_ptr->offset); in sdioh_iovar_op()
938 int_val = sdstd_rreg(si, sd_ptr->offset); in sdioh_iovar_op()
946 /* XXX Should copy for alignment reasons */ in sdioh_iovar_op()
949 if (sd_ptr->offset < SD_SysAddr || sd_ptr->offset > SD3_WL_BT_reset_register) { in sdioh_iovar_op()
950 sd_err(("%s: bad offset 0x%x\n", __FUNCTION__, sd_ptr->offset)); in sdioh_iovar_op()
955 sd_trace(("%s: wreg%d value 0x%08x at offset %d\n", __FUNCTION__, sd_ptr->value, in sdioh_iovar_op()
956 (sd_ptr->offset & 1) ? 8 : ((sd_ptr->offset & 2) ? 16 : 32), in sdioh_iovar_op()
957 sd_ptr->offset)); in sdioh_iovar_op()
958 if (sd_ptr->offset & 1) in sdioh_iovar_op()
959 sdstd_wreg8(si, sd_ptr->offset, (uint8)sd_ptr->value); in sdioh_iovar_op()
960 else if (sd_ptr->offset & 2) in sdioh_iovar_op()
961 sdstd_wreg16(si, sd_ptr->offset, (uint16)sd_ptr->value); in sdioh_iovar_op()
963 sdstd_wreg(si, sd_ptr->offset, (uint32)sd_ptr->value); in sdioh_iovar_op()
970 /* XXX Should copy for alignment reasons */ in sdioh_iovar_op()
974 if (sdioh_cfg_read(si, sd_ptr->func, sd_ptr->offset, &data)) { in sdioh_iovar_op()
986 /* XXX Should copy for alignment reasons */ in sdioh_iovar_op()
988 uint8 data = (uint8)sd_ptr->value; in sdioh_iovar_op()
990 if (sdioh_cfg_write(si, sd_ptr->func, sd_ptr->offset, &data)) { in sdioh_iovar_op()
1024 si->sd3_tuning_disable = (bool)int_val; in sdioh_iovar_op()
1033 /* XXX Remove protective lock after clients all clean... */ in sdioh_iovar_op()
1065 if (!sd->func_cis_ptr[func]) { in sdioh_cis_read()
1073 offset = sd->func_cis_ptr[func] + count; in sdioh_cis_read()
1193 sd->glom_info.dma_buf_arr[sd->glom_info.count] = frame; in sdioh_glom_post()
1194 sd->glom_info.nbytes[sd->glom_info.count] = len; in sdioh_glom_post()
1196 if (sd->txglom_mode == SDPCM_TXGLOM_MDESC) { in sdioh_glom_post()
1197 sd->glom_info.dma_phys_arr[sd->glom_info.count] = DMA_MAP(sd->osh, in sdioh_glom_post()
1202 sd->glom_info.count++; in sdioh_glom_post()
1210 if (sd->txglom_mode == SDPCM_TXGLOM_MDESC) { in sdioh_glom_clear()
1211 for (i = 0; i < sd->glom_info.count; i++) { in sdioh_glom_clear()
1212 DMA_UNMAP(sd->osh, in sdioh_glom_clear()
1213 sd->glom_info.dma_phys_arr[i], in sdioh_glom_clear()
1214 sd->glom_info.nbytes[i], in sdioh_glom_clear()
1218 sd->glom_info.count = 0; in sdioh_glom_clear()
1222 sdioh_set_mode(sdioh_info_t *sd, uint mode) in sdioh_set_mode() argument
1224 if (mode == SDPCM_TXGLOM_CPY) in sdioh_set_mode()
1225 sd->txglom_mode = mode; in sdioh_set_mode()
1226 else if ((mode == SDPCM_TXGLOM_MDESC) && (sd->version == HOST_CONTR_VER_3)) in sdioh_set_mode()
1227 sd->txglom_mode = mode; in sdioh_set_mode()
1229 return (sd->txglom_mode); in sdioh_set_mode()
1248 bool local_blockmode = sd->sd_blockmode; in sdioh_request_buffer()
1262 ASSERT(sd->client_block_size[func]); in sdioh_request_buffer()
1267 sdioh_glom_post(sd, PKTDATA(sd->osh, pkt), pkt, PKTLEN(sd->osh, pkt)); in sdioh_request_buffer()
1268 pkt = PKTNEXT(sd->osh, pkt); in sdioh_request_buffer()
1274 buflen_u, sd->r_cnt, sd->t_cnt, pkt)); in sdioh_request_buffer()
1286 if ((sd->version == HOST_CONTR_VER_3) && sd_txglom) in sdioh_request_buffer()
1293 if (buflen > sd->client_block_size[func]) in sdioh_request_buffer()
1294 len = (len/sd->client_block_size[func]) * in sdioh_request_buffer()
1295 sd->client_block_size[func]; in sdioh_request_buffer()
1296 /* XXX Arasan trashes 3-byte transfers, WAR to add one byte extra. */ in sdioh_request_buffer()
1297 /* XXX In Case of SDIO3.0 DDR50 mode if no of bytes to be in sdioh_request_buffer()
1306 if ((localbuf = (uint8 *)MALLOC(sd->osh, len)) == NULL) { in sdioh_request_buffer()
1308 MALLOCED(sd->osh))); in sdioh_request_buffer()
1316 /* Byte mode: One block at a time */ in sdioh_request_buffer()
1317 len = MIN(sd->client_block_size[func], buflen); in sdioh_request_buffer()
1324 /* XXX Restore len and buffer pointer WAR'ed for Arasan 3-byte transfer problem */ in sdioh_request_buffer()
1325 /* XXX WAR for SDIO3.0 DDR50 mode. */ in sdioh_request_buffer()
1327 MFREE(sd->osh, localbuf, len); in sdioh_request_buffer()
1328 len--; in sdioh_request_buffer()
1338 buflen -= len; in sdioh_request_buffer()
1345 if (sd->glom_info.count != 0) in sdioh_request_buffer()
1375 gpio -= SDH_GPIO16; in sdioh_gpioouten()
1394 gpio -= SDH_GPIO16; in sdioh_gpioout()
1416 gpio -= SDH_GPIO16; in sdioh_gpioin()
1458 cmd_arg = SFIELD(cmd_arg, CMD14_RCA, sd->card_rca); in sdioh_sleep()
1467 while (retry-- > 0) { in sdioh_sleep()
1486 cmd_arg = SFIELD(0, CMD7_RCA, sd->card_rca); in sdioh_sleep()
1508 /* XXX Copied guts of request_byte and cmd_issue. Might make sense to fold this into
1510 * keeping it separate is better -- if called internally on command failure it's less
1544 /* XXX Copied from cmd_issue(), but no SPI response handling! */ in sdstd_abort()
1545 if (sd->sd_mode == SDIOH_MODE_SPI) { in sdstd_abort()
1551 /* XXX For a single-threaded driver, what circumstances would result in sdstd_abort()
1561 if (!--retries) { in sdstd_abort()
1593 /* In interrupt mode return, expect later CMD_COMPLETE interrupt */ in sdstd_abort()
1594 if (!sd->polled_mode) in sdstd_abort()
1601 } while (--retries && in sdstd_abort()
1617 SW_RESET_CMD)) && retries--); in sdstd_abort()
1648 SW_RESET_DAT)) && retries--); in sdstd_abort()
1658 /* XXX But what about busy timeout? Response valid? */ in sdstd_abort()
1699 /* XXX As per spec 3.7.1 (and to be safe) do the resets here */ in sdstd_abort()
1708 } while (--retries); in sdstd_abort()
1763 /* XXX - Getting bogus errors under QT in sdstd_check_errs()
1764 * XXX - Not sure why; Just ignore for now in sdstd_check_errs()
1792 for (retries = RETRIES_LARGE; retries; retries--) in sdstd_check_errs()
1807 for (retries = RETRIES_LARGE; retries; retries--) in sdstd_check_errs()
1860 if (client_reset && (sd->adapter_slot != -1)) { in sdstd_reset()
1865 sd->card_rca = 0; in sdstd_reset()
1874 } while ((sdstd_rreg8(sd, SD_SoftwareReset) & regval) && retries--); in sdstd_reset()
1882 /* A reset should reset bus back to 1 bit mode */ in sdstd_reset()
1883 sd->sd_mode = SDIOH_MODE_SD1; in sdstd_reset()
1884 sdstd_set_dma_mode(sd, sd->sd_dma_mode); in sdstd_reset()
1894 sd_trace(("%s: %d\n", __FUNCTION__, sd->use_client_ints)); in sdstd_devintr_off()
1895 if (sd->use_client_ints) { in sdstd_devintr_off()
1896 sd->intmask &= ~CLIENT_INTR; in sdstd_devintr_off()
1897 sdstd_wreg16(sd, SD_IntrSignalEnable, sd->intmask); in sdstd_devintr_off()
1906 ASSERT(sd->lockcount == 0); in sdstd_devintr_on()
1907 sd_trace(("%s: %d\n", __FUNCTION__, sd->use_client_ints)); in sdstd_devintr_on()
1908 if (sd->use_client_ints) { in sdstd_devintr_on()
1909 if (sd->version < HOST_CONTR_VER_3) { in sdstd_devintr_on()
1915 sd->intmask |= CLIENT_INTR; in sdstd_devintr_on()
1916 sdstd_wreg16(sd, SD_IntrSignalEnable, sd->intmask); in sdstd_devintr_on()
1931 sd->intmask |= norm; in sdstd_intrs_on()
1932 sdstd_wreg16(sd, SD_IntrSignalEnable, sd->intmask); in sdstd_intrs_on()
1945 sd->intmask &= ~norm; in sdstd_intrs_off()
1946 sdstd_wreg16(sd, SD_IntrSignalEnable, sd->intmask); in sdstd_intrs_off()
1967 if ((OSL_PCI_READ_CONFIG(sd->osh, PCI_CFG_VID, 4) & 0xFFFF) == VENDOR_SI_IMAGE) { in sdstd_host_init()
1969 sd->controller_type = SDIOH_TYPE_ARASAN_HDK; in sdstd_host_init()
1972 sd->sd_dma_mode = DMA_MODE_SDMA; in sdstd_host_init()
1973 } else if ((OSL_PCI_READ_CONFIG(sd->osh, PCI_CFG_VID, 4) & 0xFFFF) == VENDOR_BROADCOM) { in sdstd_host_init()
1975 sd->controller_type = SDIOH_TYPE_BCM27XX; in sdstd_host_init()
1977 } else if ((OSL_PCI_READ_CONFIG(sd->osh, PCI_CFG_VID, 4) & 0xFFFF) == VENDOR_TI) { in sdstd_host_init()
1979 sd->controller_type = SDIOH_TYPE_TI_PCIXX21; in sdstd_host_init()
1981 } else if ((OSL_PCI_READ_CONFIG(sd->osh, PCI_CFG_VID, 4) & 0xFFFF) == VENDOR_RICOH) { in sdstd_host_init()
1984 sd->controller_type = SDIOH_TYPE_RICOH_R5C822; in sdstd_host_init()
1986 } else if ((OSL_PCI_READ_CONFIG(sd->osh, PCI_CFG_VID, 4) & 0xFFFF) == VENDOR_JMICRON) { in sdstd_host_init()
1989 sd->controller_type = SDIOH_TYPE_JMICRON; in sdstd_host_init()
1992 } else if ((OSL_PCI_READ_CONFIG(sd->osh, PCI_CFG_VID, 4) & 0xFFFF) == VENDOR_JINVANI) { in sdstd_host_init()
1995 sd->controller_type = SDIOH_TYPE_JINVANI_GOLD; in sdstd_host_init()
2006 first_bar = OSL_PCI_READ_CONFIG(sd->osh, SD_SlotInfo, 4) & 0x7; in sdstd_host_init()
2007 num_slots = (OSL_PCI_READ_CONFIG(sd->osh, SD_SlotInfo, 4) & 0xff) >> 4; in sdstd_host_init()
2011 /* XXX Since the sdio20h core does not present the proper SD_SlotInfo in sdstd_host_init()
2015 if (OSL_PCI_READ_CONFIG(sd->osh, PCI_CFG_VID, 4) == in sdstd_host_init()
2019 OSL_PCI_WRITE_CONFIG(sd->osh, PCI_BAR0_WIN, 4, 0x18001000); in sdstd_host_init()
2027 sd->sd_dma_mode = DMA_MODE_ADMA2; in sdstd_host_init()
2033 if (sd->mem_space) { in sdstd_host_init()
2034 sdstd_reg_unmap(sd->osh, (ulong)sd->mem_space, SDIOH_REG_WINSZ); in sdstd_host_init()
2035 sd->mem_space = NULL; in sdstd_host_init()
2038 full_slot = -1; in sdstd_host_init()
2041 /* XXX :Ugly define, is there a better way */ in sdstd_host_init()
2044 bar.LowPart = OSL_PCI_READ_CONFIG(sd->osh, PCI_CFG_BAR0 in sdstd_host_init()
2046 sd->mem_space = (volatile char *)sdstd_reg_map(sd->osh, in sdstd_host_init()
2049 bar = OSL_PCI_READ_CONFIG(sd->osh, PCI_CFG_BAR0 + (4*(slot + first_bar)), 4); in sdstd_host_init()
2050 sd->mem_space = (volatile char *)sdstd_reg_map(sd->osh, in sdstd_host_init()
2054 sd->adapter_slot = -1; in sdstd_host_init()
2070 if (sd->mem_space) { in sdstd_host_init()
2071 sdstd_reg_unmap(sd->osh, (ulong)sd->mem_space, SDIOH_REG_WINSZ); in sdstd_host_init()
2072 sd->mem_space = NULL; in sdstd_host_init()
2078 return -1; in sdstd_host_init()
2081 /* XXX :Ugly define, is there a better way */ in sdstd_host_init()
2084 bar.LowPart = OSL_PCI_READ_CONFIG(sd->osh, PCI_CFG_BAR0 + (4*(full_slot + first_bar)), 4); in sdstd_host_init()
2085 sd->mem_space = (volatile char *)sdstd_reg_map(sd->osh, (int32)&bar, SDIOH_REG_WINSZ); in sdstd_host_init()
2087 bar = OSL_PCI_READ_CONFIG(sd->osh, PCI_CFG_BAR0 + (4*(full_slot + first_bar)), 4); in sdstd_host_init()
2088 sd->mem_space = (volatile char *)sdstd_reg_map(sd->osh, (uintptr)bar, SDIOH_REG_WINSZ); in sdstd_host_init()
2094 OSL_PCI_READ_CONFIG(sd->osh, PCI_CFG_BAR0 + (4*(full_slot + first_bar)), 4), in sdstd_host_init()
2095 sd->mem_space)); in sdstd_host_init()
2097 sd->adapter_slot = full_slot; in sdstd_host_init()
2099 sd->version = sdstd_rreg16(sd, SD_HostControllerVersion) & 0xFF; in sdstd_host_init()
2100 switch (sd->version) { in sdstd_host_init()
2115 __FUNCTION__, sd->version)); in sdstd_host_init()
2119 sd->caps = sdstd_rreg(sd, SD_Capabilities); /* Cache this for later use */ in sdstd_host_init()
2121 sd->caps3 = sdstd_rreg(sd, SD_Capabilities3); /* Cache this for later use */ in sdstd_host_init()
2122 sd3_trace(("sd3: %s: caps: 0x%x; MCCap:0x%x\n", __FUNCTION__, sd->caps, sd->curr_caps)); in sdstd_host_init()
2123 sd3_trace(("sd3: %s: caps3: 0x%x\n", __FUNCTION__, sd->caps3)); in sdstd_host_init()
2124 sd->curr_caps = sdstd_rreg(sd, SD_MaxCurCap); in sdstd_host_init()
2126 sd_info(("%s: caps: 0x%x; MCCap:0x%x\n", __FUNCTION__, sd->caps, sd->curr_caps)); in sdstd_host_init()
2128 sdstd_set_dma_mode(sd, sd->sd_dma_mode); in sdstd_host_init()
2131 if (OSL_PCI_READ_CONFIG(sd->osh, PCI_CFG_VID, 4) == in sdstd_host_init()
2136 if (GFIELD(sd->caps, CAP_MAXBLOCK) == 0x3) { in sdstd_host_init()
2140 512 << GFIELD(sd->caps, CAP_MAXBLOCK))); in sdstd_host_init()
2143 sd_info(("SD HOST CAPS: 64-bit DMA is %ssupported.\n", in sdstd_host_init()
2144 GFIELD(sd->caps, CAP_64BIT_HOST) ? "" : "not ")); in sdstd_host_init()
2146 GFIELD(sd->caps, CAP_SUSPEND) ? "" : "not ")); in sdstd_host_init()
2149 if (GFIELD(sd->caps, CAP_VOLT_3_3)) { in sdstd_host_init()
2151 if (GFIELD(sd->curr_caps, CAP_CURR_3_3)) { in sdstd_host_init()
2152 sd_err(("@%dmA\n", 4*GFIELD(sd->curr_caps, CAP_CURR_3_3))); in sdstd_host_init()
2155 if (GFIELD(sd->caps, CAP_VOLT_3_0)) { in sdstd_host_init()
2157 if (GFIELD(sd->curr_caps, CAP_CURR_3_0)) { in sdstd_host_init()
2158 sd_err(("@%dmA\n", 4*GFIELD(sd->curr_caps, CAP_CURR_3_0))); in sdstd_host_init()
2161 if (GFIELD(sd->caps, CAP_VOLT_1_8)) { in sdstd_host_init()
2163 if (GFIELD(sd->curr_caps, CAP_CURR_1_8)) { in sdstd_host_init()
2164 sd_err(("@%dmA\n", 4*GFIELD(sd->curr_caps, CAP_CURR_1_8))); in sdstd_host_init()
2172 /* Read SD4/SD1 mode */ in sdstd_host_init()
2175 sd_err(("%s: Host cntrlr already in 4 bit mode: 0x%x\n", in sdstd_host_init()
2180 /* Default power on mode is SD1 */ in sdstd_host_init()
2181 sd->sd_mode = SDIOH_MODE_SD1; in sdstd_host_init()
2182 sd->polled_mode = TRUE; in sdstd_host_init()
2183 sd->host_init_done = TRUE; in sdstd_host_init()
2184 sd->card_init_done = FALSE; in sdstd_host_init()
2185 sd->adapter_slot = full_slot; in sdstd_host_init()
2187 /* XXX: If sd_uhsimode is disabled, which means that, use the HC in SDIO 2.0 mode. */ in sdstd_host_init()
2189 sd->version = HOST_CONTR_VER_2; in sdstd_host_init()
2193 if (sd->version == HOST_CONTR_VER_3) { in sdstd_host_init()
2204 if ((GFIELD(sd->caps, CAP_VOLT_1_8)) && in sdstd_host_init()
2205 (GFIELD(sd->caps3, CAP3_SDR50_SUP) || in sdstd_host_init()
2206 GFIELD(sd->caps3, CAP3_SDR104_SUP) || in sdstd_host_init()
2207 GFIELD(sd->caps3, CAP3_DDR50_SUP))) in sdstd_host_init()
2208 sd->host_UHSISupported = 1; in sdstd_host_init()
2217 intmask = OSL_PCI_READ_CONFIG(sd->osh, PCI_INT_MASK, 4); in sdstd_host_init()
2219 OSL_PCI_WRITE_CONFIG(sd->osh, PCI_INT_MASK, 4, intmask); in sdstd_host_init()
2244 } while ((!GFIELD(*cmd_rsp, RSP4_CARD_READY)) && --retries); in get_ocr()
2264 parse_caps(sd->caps, caps_buf, 500); in sdstd_client_init()
2269 sd_trace(("%s: Powering up slot %d\n", __FUNCTION__, sd->adapter_slot)); in sdstd_client_init()
2280 if (!sd->host_UHSISupported) in sdstd_client_init()
2293 if (sd->host_UHSISupported) { in sdstd_client_init()
2294 /* when HC is started for SDIO 3.0 mode, start in lowest voltage mode first. */ in sdstd_client_init()
2308 /* XXX legacy driver: start in highest voltage mode first. in sdstd_client_init()
2317 if (sd->num_funcs == 0) { in sdstd_client_init()
2322 /* In SPI mode, issue CMD0 first */ in sdstd_client_init()
2323 if (sd->sd_mode == SDIOH_MODE_SPI) { in sdstd_client_init()
2332 if (sd->sd_mode != SDIOH_MODE_SPI) { in sdstd_client_init()
2355 sd->card_rca = GFIELD(cmd_rsp, RSP6_IO_RCA); in sdstd_client_init()
2356 sd_info(("RCA is 0x%x\n", sd->card_rca)); in sdstd_client_init()
2362 cmd_arg = SFIELD(0, CMD7_RCA, sd->card_rca); in sdstd_client_init()
2376 /* Disable default/power-up device Card Detect (CD) pull up resistor on DAT3 in sdstd_client_init()
2401 if (sd->num_funcs >= 2) { in sdstd_client_init()
2402 /* XXX Device side can't handle 512 yet */ in sdstd_client_init()
2416 /* Switch to High-speed clocking mode if both host and device support it */ in sdstd_client_init()
2428 sd->card_init_done = TRUE; in sdstd_client_init()
2437 /* After configuring for High-Speed mode, set the desired clock rate. */ in sdstd_clock_wrapper()
2452 if (sd->card_UHSI_voltage_Supported) { in sdstd_3_clock_wrapper()
2457 if (retclk == -1) { in sdstd_3_clock_wrapper()
2462 if (retclk == -1) { in sdstd_3_clock_wrapper()
2464 * High speed/legacy mode if possible. in sdstd_3_clock_wrapper()
2474 "auto mode\n", __FUNCTION__)); in sdstd_3_clock_wrapper()
2479 if (retclk != -1) { in sdstd_3_clock_wrapper()
2488 /* try legacy mode */ in sdstd_3_clock_wrapper()
2495 sd_info(("%s: Legacy Mode Clock\n", __FUNCTION__)); in sdstd_3_clock_wrapper()
2496 /* try legacy mode */ in sdstd_3_clock_wrapper()
2518 if (!sd->sd3_tuning_reqd) { in sdstd_3_clk_tuning()
2659 sd->intmask &= ~HC_INTR_RETUNING; in sdstd_3_disable_retuning_int()
2701 if (HOST_SDR_UNSUPP == sd->global_UHSI_Supp) { in sdstd_3_set_highspeed_uhsi_mode()
2731 sd_info(("Device supports High-Speed mode.\n")); in sdstd_3_set_highspeed_uhsi_mode()
2754 sd_err(("Device does not support High-Speed Mode.\n")); in sdstd_3_set_highspeed_uhsi_mode()
2761 /* set to HighSpeed mode */ in sdstd_3_set_highspeed_uhsi_mode()
2766 /* set UHS Mode select in HC2 and also set preset */ in sdstd_3_set_highspeed_uhsi_mode()
2794 sd->sd3_tuning_reqd = TRUE; in sdstd_3_set_highspeed_uhsi_mode()
2799 sd->sd3_tuning_reqd = FALSE; in sdstd_3_set_highspeed_uhsi_mode()
2810 if (!sd->sd3_tuning_disable && sd->sd3_tuning_reqd) { in sdstd_3_check_and_do_tuning()
2813 if (sd->sd3_tun_state == TUNING_ONGOING) { in sdstd_3_check_and_do_tuning()
2817 HOSTCtrl2_EXEC_TUNING)) && retries--) { in sdstd_3_check_and_do_tuning()
2828 } else if (sd->sd3_tun_state == TUNING_START) { in sdstd_3_check_and_do_tuning()
2835 if (sd->sd3_tun_state == TUNING_START_AFTER_DAT) { in sdstd_3_check_and_do_tuning()
2843 /* Need to run this function in interrupt-disabled context */
2849 if ((sd->sd3_tun_state == TUNING_START) || in sdstd_3_check_and_set_retuning()
2850 (sd->sd3_tun_state == TUNING_ONGOING) || in sdstd_3_check_and_set_retuning()
2851 (sd->sd3_tun_state == TUNING_START_AFTER_DAT)) { in sdstd_3_check_and_set_retuning()
2856 if (sd->sd3_dat_state == DATA_TRANSFER_IDLE) { in sdstd_3_check_and_set_retuning()
2857 sd->sd3_tun_state = TUNING_START; /* tuning to be started by the tasklet */ in sdstd_3_check_and_set_retuning()
2861 sd->sd3_tun_state = TUNING_START_AFTER_DAT; in sdstd_3_check_and_set_retuning()
2868 return sd->sd3_dat_state; in sdstd_3_get_data_state()
2873 sd->sd3_dat_state = state; in sdstd_3_set_data_state()
2878 return sd->sd3_tun_state; in sdstd_3_get_tune_state()
2883 sd->sd3_tun_state = state; in sdstd_3_set_tune_state()
2889 return GFIELD(sd->caps3, CAP3_RETUNING_TC); in sdstd_3_get_tuning_exp()
2901 in preset value, which will be selected by requested UHSI mode
2903 clk mode: valid values: SD3CLKMODE_2_SDR50, SD3CLKMODE_3_SDR104,
2960 ds_offset = (((int)DRVSTRN_MAX_CHAR - in sdstd_3_get_matching_drvstrn()
2963 ds_offset = MAX_DTS_INDEX - ds_offset; in sdstd_3_get_matching_drvstrn()
2985 /* TBD check for sd3_requested_clkmode : -1 also. */ in sdstd_3_get_matching_drvstrn()
2992 /* Returns a matching UHSI clk speed is found. If not, returns -1.
2993 Also, if sd3_requested_clkmode is -1, finds the closest max match clk and returns.
3006 sd->global_UHSI_Supp = HOST_SDR_UNSUPP; in sdstd_3_get_matching_uhsi_clkmode()
3011 sd->global_UHSI_Supp = HOST_SDR_12_25; in sdstd_3_get_matching_uhsi_clkmode()
3018 return -1; in sdstd_3_get_matching_uhsi_clkmode()
3025 speedmask <<= (sd3_requested_clkmode - SD3CLKMODE_2_SDR50); in sdstd_3_get_matching_uhsi_clkmode()
3028 if (!(GFIELD(sd->caps3, CAP3_30CLKCAP) & speedmask)) { in sdstd_3_get_matching_uhsi_clkmode()
3029 sd_err(("%s:HC does not support req 3.0 UHSI mode." in sdstd_3_get_matching_uhsi_clkmode()
3031 sd3_requested_clkmode, GFIELD(sd->caps3, CAP3_30CLKCAP))); in sdstd_3_get_matching_uhsi_clkmode()
3032 return -1; in sdstd_3_get_matching_uhsi_clkmode()
3037 sd_err(("%s:Card does not support req 3.0 UHSI mode. requested:%d;" in sdstd_3_get_matching_uhsi_clkmode()
3040 return -1; in sdstd_3_get_matching_uhsi_clkmode()
3045 requested UHSI mode in sdstd_3_get_matching_uhsi_clkmode()
3051 return -1; in sdstd_3_get_matching_uhsi_clkmode()
3054 sd->global_UHSI_Supp = HOST_SDR_50_104_DDR; in sdstd_3_get_matching_uhsi_clkmode()
3059 /* sd->global_UHSI_Supp = TRUE; on success */ in sdstd_3_get_matching_uhsi_clkmode()
3060 return -1; in sdstd_3_get_matching_uhsi_clkmode()
3147 /* The Jinvani SD Gold Host forces the highest clock rate in high-speed mode */ in sdstd_set_highspeed_mode()
3148 /* Only enable high-speed mode if the SD clock divisor is 1. */ in sdstd_set_highspeed_mode()
3149 if (sd->controller_type == SDIOH_TYPE_JINVANI_GOLD) { in sdstd_set_highspeed_mode()
3157 if (sd_hiok && (GFIELD(sd->caps, CAP_HIGHSPEED)) == 0) { in sdstd_set_highspeed_mode()
3158 sd_err(("Host Controller does not support hi-speed mode.\n")); in sdstd_set_highspeed_mode()
3162 sd_info(("Attempting to enable High-Speed mode.\n")); in sdstd_set_highspeed_mode()
3169 sd_info(("Device supports High-Speed mode.\n")); in sdstd_set_highspeed_mode()
3189 sd_err(("High-speed clocking mode enabled.\n")); in sdstd_set_highspeed_mode()
3192 sd_err(("Device does not support High-Speed Mode.\n")); in sdstd_set_highspeed_mode()
3209 sd_err(("High-speed clocking mode disabled.\n")); in sdstd_set_highspeed_mode()
3213 if ((sd->host_UHSISupported) && (sd->card_UHSI_voltage_Supported)) { in sdstd_set_highspeed_mode()
3242 /* Select DMA Mode:
3243 * If dma_mode == DMA_MODE_AUTO, pick the "best" mode.
3244 * Otherwise, pick the selected mode if supported.
3245 * If not supported, use PIO mode.
3251 int8 prev_dma_mode = sd->sd_dma_mode; in sdstd_set_dma_mode()
3255 sd_dma(("%s: Selecting best DMA mode supported by controller.\n", in sdstd_set_dma_mode()
3257 if (GFIELD(sd->caps, CAP_ADMA2)) { in sdstd_set_dma_mode()
3258 sd->sd_dma_mode = DMA_MODE_ADMA2; in sdstd_set_dma_mode()
3260 } else if (GFIELD(sd->caps, CAP_ADMA1)) { in sdstd_set_dma_mode()
3261 sd->sd_dma_mode = DMA_MODE_ADMA1; in sdstd_set_dma_mode()
3263 } else if (GFIELD(sd->caps, CAP_DMA)) { in sdstd_set_dma_mode()
3264 sd->sd_dma_mode = DMA_MODE_SDMA; in sdstd_set_dma_mode()
3266 sd->sd_dma_mode = DMA_MODE_NONE; in sdstd_set_dma_mode()
3270 sd->sd_dma_mode = DMA_MODE_NONE; in sdstd_set_dma_mode()
3273 if (GFIELD(sd->caps, CAP_DMA)) { in sdstd_set_dma_mode()
3274 sd->sd_dma_mode = DMA_MODE_SDMA; in sdstd_set_dma_mode()
3277 sd->sd_dma_mode = DMA_MODE_NONE; in sdstd_set_dma_mode()
3281 if (GFIELD(sd->caps, CAP_ADMA1)) { in sdstd_set_dma_mode()
3282 sd->sd_dma_mode = DMA_MODE_ADMA1; in sdstd_set_dma_mode()
3286 sd->sd_dma_mode = DMA_MODE_NONE; in sdstd_set_dma_mode()
3290 if (GFIELD(sd->caps, CAP_ADMA2)) { in sdstd_set_dma_mode()
3291 sd->sd_dma_mode = DMA_MODE_ADMA2; in sdstd_set_dma_mode()
3295 sd->sd_dma_mode = DMA_MODE_NONE; in sdstd_set_dma_mode()
3300 sd->sd_dma_mode = DMA_MODE_NONE; in sdstd_set_dma_mode()
3303 sd_err(("%s: Unsupported DMA Mode %d requested.\n", __FUNCTION__, in sdstd_set_dma_mode()
3305 sd->sd_dma_mode = DMA_MODE_NONE; in sdstd_set_dma_mode()
3312 sd_err(("%s: %s mode selected.\n", __FUNCTION__, dma_mode_description[sd->sd_dma_mode])); in sdstd_set_dma_mode()
3437 return (data - buf); in parse_state()
3462 return (data - buf); in parse_caps()
3467 /* XXX Per SDIO Host Controller Spec section 3.2.1
3485 if (sd->host_UHSISupported) { in sdstd_start_clock()
3499 if ((new_sd_divisor & (new_sd_divisor-1)) || in sdstd_start_clock()
3511 if (sd->controller_type == SDIOH_TYPE_JINVANI_GOLD) { in sdstd_start_clock()
3517 if (sd->host_UHSISupported) { in sdstd_start_clock()
3519 * bits 0-7 are in 15-8 and 9-8 are in 7-6 of clkctrl in sdstd_start_clock()
3536 __FUNCTION__, GFIELD(sd->caps, CAP_BASECLK)*1000000/new_sd_divisor)); in sdstd_start_clock()
3538 sd_err(("Using Primary Clock Freq of %d MHz\n", GFIELD(sd->caps, CAP_BASECLK))); in sdstd_start_clock()
3539 sd_info(("Primary Clock Freq = %d MHz\n", GFIELD(sd->caps, CAP_BASECLK))); in sdstd_start_clock()
3540 if (GFIELD(sd->caps, CAP_TO_CLKFREQ) == 50) { in sdstd_start_clock()
3544 } else if (GFIELD(sd->caps, CAP_TO_CLKFREQ) == 48) { in sdstd_start_clock()
3548 } else if (GFIELD(sd->caps, CAP_TO_CLKFREQ) == 33) { in sdstd_start_clock()
3552 } else if (GFIELD(sd->caps, CAP_TO_CLKFREQ) == 31) { in sdstd_start_clock()
3556 } else if (GFIELD(sd->caps, CAP_TO_CLKFREQ) == 8) { in sdstd_start_clock()
3560 } else if (sd->controller_type == SDIOH_TYPE_BCM27XX) { in sdstd_start_clock()
3561 /* XXX - BCM 27XX Standard Host Controller returns 0 for CLKFREQ */ in sdstd_start_clock()
3564 GFIELD(sd->caps, CAP_BASECLK))); in sdstd_start_clock()
3594 if (GFIELD(sd->caps, CAP_BASECLK) < 50) in sdstd_start_clock()
3603 toval -= 1; in sdstd_start_clock()
3615 /* XXX: turn off timeout INT, it resets clk ctrl bit */ in sdstd_start_clock()
3627 /* XXX Per SDIO Host Controller Spec 3.3
3652 sd->card_UHSI_voltage_Supported = FALSE; in sdstd_start_power()
3672 if (GFIELD(sd->caps, CAP_VOLT_1_8)) { in sdstd_start_power()
3686 if (GFIELD(sd->caps, CAP_VOLT_3_0)) { in sdstd_start_power()
3699 if (GFIELD(sd->caps, CAP_VOLT_3_3)) { in sdstd_start_power()
3710 /* XXX in sdstd_start_power()
3729 if ((sd->version == HOST_CONTR_VER_3) && (volts == 5)) { in sdstd_start_power()
3743 baseclk = GFIELD(sd->caps, CAP_BASECLK); in sdstd_start_power()
3746 if (sd->host_UHSISupported) { in sdstd_start_power()
3749 if (GFIELD(sd->caps3, CAP3_CLK_MULT) != 0) { in sdstd_start_power()
3797 /* Verify that the card supports I/O mode */ in sdstd_start_power()
3802 sd->num_funcs = GFIELD(cmd_rsp, RSP4_NUM_FUNCS); in sdstd_start_power()
3805 * so look for 3.2-3.3 Volts and also 3.3-3.4 volts. in sdstd_start_power()
3808 /* XXX Pg 10 SDIO spec v1.10 */ in sdstd_start_power()
3817 if ((sd->host_UHSISupported) && (volts == 5)) { in sdstd_start_power()
3825 if ((sd->host_UHSISupported)) { in sdstd_start_power()
3835 sd->card_UHSI_voltage_Supported = TRUE; in sdstd_start_power()
3845 * sd->card_UHSI_voltage_Supported = TRUE; in sdstd_start_power()
3852 __FUNCTION__, sd->host_UHSISupported, volts)); in sdstd_start_power()
3869 if (sd->sd_mode == new_mode) { in sdstd_bus_width()
3879 sd_info(("Changing to SD4 Mode\n")); in sdstd_bus_width()
3882 sd_info(("Changing to SD1 Mode\n")); in sdstd_bus_width()
3884 sd_err(("SPI Mode not supported by Standard Host Controller\n")); in sdstd_bus_width()
3890 if (sd->host_UHSISupported) { in sdstd_bus_width()
3903 (GFIELD(sd->caps, CAP_ASYNCINT_SUP))) { in sdstd_bus_width()
3930 sd->sd_mode = new_mode; in sdstd_bus_width()
3939 sd->sd3_tuning_reqd = FALSE; in sdstd_driver_init()
3940 sd->sd3_tuning_disable = FALSE; in sdstd_driver_init()
3946 if ((sd->controller_type == SDIOH_TYPE_RICOH_R5C822) && (sd->version == HOST_CONTR_VER_3)) in sdstd_driver_init()
3960 sd->sd3_tuning_reqd = TRUE; in sdstd_driver_init()
3966 if (GFIELD(sd->caps3, CAP3_RETUNING_MODES)) { in sdstd_driver_init()
3968 sd->intmask |= HC_INTR_RETUNING; in sdstd_driver_init()
3969 sdstd_wreg16(sd, SD_IntrSignalEnable, sd->intmask); in sdstd_driver_init()
3994 /* Only the lower 17-bits are valid */ in sdstd_get_cisaddr()
4011 sd->com_cis_ptr = sdstd_get_cisaddr(sd, SDIOD_CCCR_CISPTR_0); in sdstd_card_enablefuncs()
4012 sd->func_cis_ptr[0] = sd->com_cis_ptr; in sdstd_card_enablefuncs()
4013 sd_info(("%s: Card's Common CIS Ptr = 0x%x\n", __FUNCTION__, sd->com_cis_ptr)); in sdstd_card_enablefuncs()
4017 func <= sd->num_funcs; func++, fbraddr += SDIOD_FBR_SIZE) { in sdstd_card_enablefuncs()
4018 sd->func_cis_ptr[func] = sdstd_get_cisaddr(sd, SDIOD_FBR_CISPTR_0 + fbraddr); in sdstd_card_enablefuncs()
4020 __FUNCTION__, func, sd->func_cis_ptr[func])); in sdstd_card_enablefuncs()
4078 cmd_arg = SFIELD(cmd_arg, CMD53_OP_CODE, 1); /* XXX SDIO spec v 1.10, Sec 5.3 */ in sdstd_card_regread()
4084 sd->data_xfer_count = regsize; in sdstd_card_regread()
4103 if (sd->polled_mode) { in sdstd_card_regread()
4111 } while (--retries && (GFIELD(int_reg, INTSTAT_BUF_READ_READY) == 0)); in sdstd_card_regread()
4137 } while (--retries && (GFIELD(int_reg, INTSTAT_XFER_COMPLETE) == 0)); in sdstd_card_regread()
4155 if (sd->polled_mode) { in sdstd_card_regread()
4168 cur_int = raw_int & sd->intmask; in check_client_intr()
4171 /* Not an error -- might share interrupts... */ in check_client_intr()
4183 if (sd->client_intr_enabled && sd->use_client_ints) { in check_client_intr()
4184 sd->intrcount++; in check_client_intr()
4185 ASSERT(sd->intr_handler); in check_client_intr()
4186 ASSERT(sd->intr_handler_arg); in check_client_intr()
4187 (sd->intr_handler)(sd->intr_handler_arg); in check_client_intr()
4190 __FUNCTION__, sd->client_intr_enabled, sd->intr_handler)); in check_client_intr()
4200 sd->local_intrcount++; in check_client_intr()
4201 sd->got_hcint = TRUE; in check_client_intr()
4202 sd->last_intrstatus = cur_int; in check_client_intr()
4217 } while (--retries && !(int_reg & norm) && !(err_reg & err)); in sdstd_spinbits()
4219 norm |= sd->intmask; in sdstd_spinbits()
4222 sd->last_intrstatus = int_reg & norm; in sdstd_spinbits()
4252 /* XXX SDIO spec v 1.10, Sec 5.3 Not FIFO */ in sdstd_card_regwrite()
4259 sd->data_xfer_count = regsize; in sdstd_card_regwrite()
4277 if (sd->polled_mode) { in sdstd_card_regwrite()
4284 } while (--retries && (GFIELD(int_reg, INTSTAT_BUF_WRITE_READY) == 0)); in sdstd_card_regwrite()
4310 } while (--retries && (GFIELD(int_reg, INTSTAT_XFER_COMPLETE) == 0)); in sdstd_card_regwrite()
4321 sd->r_cnt, sd->t_cnt)); in sdstd_card_regwrite()
4346 Note: options: 0 - default
4347 1 - tuning option: Means that, this cmd issue is as a part
4365 if ((sdioh_info->sd_mode == SDIOH_MODE_SPI) && in sdstd_cmd_issue()
4372 while ((GFIELD(sdstd_rreg(sdioh_info, SD_PresentState), PRES_CMD_INHIBIT)) && --retries) { in sdstd_cmd_issue()
4386 case SDIOH_CMD_0: /* Set Card to Idle State - No Response */ in sdstd_cmd_issue()
4396 case SDIOH_CMD_3: /* Ask card to send RCA - Response R6 */ in sdstd_cmd_issue()
4406 case SDIOH_CMD_5: /* Send Operation condition - Response R4 */ in sdstd_cmd_issue()
4416 case SDIOH_CMD_7: /* Select card - Response R1 */ in sdstd_cmd_issue()
4426 case SDIOH_CMD_14: /* eSD Sleep - Response R1 */ in sdstd_cmd_issue()
4427 case SDIOH_CMD_11: /* Select card - Response R1 */ in sdstd_cmd_issue()
4437 case SDIOH_CMD_15: /* Set card to inactive state - Response None */ in sdstd_cmd_issue()
4447 case SDIOH_CMD_19: /* clock tuning - Response R1 */ in sdstd_cmd_issue()
4461 case SDIOH_CMD_52: /* IO R/W Direct (single byte) - Response R5 */ in sdstd_cmd_issue()
4480 sd_data(("%s: CMD53 func(%d) addr(0x%x) %s mode(%s) cnt(%d), %s\n", in sdstd_cmd_issue()
4506 ASSERT(sdioh_info->sd_blockmode); in sdstd_cmd_issue()
4509 blocksize = MIN((int)sdioh_info->data_xfer_count, in sdstd_cmd_issue()
4510 sdioh_info->client_block_size[func]); in sdstd_cmd_issue()
4513 /* data_xfer_cnt is already setup so that for multiblock mode, in sdstd_cmd_issue()
4514 * it is the entire buffer length. For non-block or single block, in sdstd_cmd_issue()
4518 switch (sdioh_info->sd_dma_mode) { in sdstd_cmd_issue()
4522 (uint32)sdioh_info->dma_phys)); in sdstd_cmd_issue()
4523 sdstd_wreg(sdioh_info, SD_SysAddr, sdioh_info->dma_phys); in sdstd_cmd_issue()
4529 /* multi-descriptor is currently used only for hc3 */ in sdstd_cmd_issue()
4530 if ((sdioh_info->glom_info.count != 0) && in sdstd_cmd_issue()
4531 (sdioh_info->txglom_mode == SDPCM_TXGLOM_MDESC)) { in sdstd_cmd_issue()
4534 i < sdioh_info->glom_info.count-1; in sdstd_cmd_issue()
4537 glom_info = &(sdioh_info->glom_info); in sdstd_cmd_issue()
4540 glom_info->dma_phys_arr[i], in sdstd_cmd_issue()
4541 glom_info->nbytes[i], in sdstd_cmd_issue()
4548 sdioh_info->glom_info.dma_phys_arr[i], in sdstd_cmd_issue()
4549 sdioh_info->glom_info.nbytes[i], in sdstd_cmd_issue()
4558 sdioh_info->dma_phys, blockcount*blocksize, in sdstd_cmd_issue()
4568 sdioh_info->adma2_dscr_phys); in sdstd_cmd_issue()
4571 sd_err(("%s: unsupported DMA mode %d.\n", in sdstd_cmd_issue()
4572 __FUNCTION__, sdioh_info->sd_dma_mode)); in sdstd_cmd_issue()
4584 if (sdioh_info->client_block_size[func] != blocksize) in sdstd_cmd_issue()
4604 PRES_DAT_INHIBIT) && --retries) in sdstd_cmd_issue()
4617 } else { /* Non block mode */ in sdstd_cmd_issue()
4620 * so, to do a 512-byte bytemode transfer, this in sdstd_cmd_issue()
4627 sdstd_wreg(sdioh_info, SD_SysAddr, sdioh_info->dma_phys); in sdstd_cmd_issue()
4629 /* PCI: Transfer Mode register 0x0c */ in sdstd_cmd_issue()
4636 /* See table 2-8 Host Controller spec ver 1.00 */ in sdstd_cmd_issue()
4642 /* XXX This should be a don't care but Arasan needs it in sdstd_cmd_issue()
4650 PRES_DAT_INHIBIT) && --retries) in sdstd_cmd_issue()
4670 if (sdioh_info->sd_mode == SDIOH_MODE_SPI) { in sdstd_cmd_issue()
4703 /* If we are in polled mode, wait for the command to complete. in sdstd_cmd_issue()
4704 * In interrupt mode, return immediately. The calling function will in sdstd_cmd_issue()
4708 if (sdioh_info->polled_mode) { in sdstd_cmd_issue()
4719 } while (--retries && in sdstd_cmd_issue()
4736 SW_RESET_CMD)) && retries--); in sdstd_cmd_issue()
4762 * XXX On entry: If single block or non-block, buffersize <= blocksize.
4792 __FUNCTION__, read ? "Rd" : "Wr", addr, nbytes, sd->r_cnt, sd->t_cnt)); in sdstd_card_buf()
4794 if (read) sd->r_cnt++; else sd->t_cnt++; in sdstd_card_buf()
4796 local_blockmode = sd->sd_blockmode; in sdstd_card_buf()
4801 if (!read && (func == SDIO_FUNC_2) && (sd->glom_info.count != 0)) { in sdstd_card_buf()
4804 for (ii = 0; ii < sd->glom_info.count; ii++) { in sdstd_card_buf()
4805 nbytes += sd->glom_info.nbytes[ii]; in sdstd_card_buf()
4807 ASSERT(nbytes <= sd->alloced_dma_size); in sdstd_card_buf()
4811 /* Don't bother with block mode on small xfers */ in sdstd_card_buf()
4812 if (nbytes < sd->client_block_size[func]) { in sdstd_card_buf()
4814 nbytes, sd->client_block_size[func])); in sdstd_card_buf()
4819 if (!read && (func == SDIO_FUNC_2) && (sd->glom_info.count != 0)) { in sdstd_card_buf()
4821 localbuf = (uint8 *)MALLOC(sd->osh, nbytes); in sdstd_card_buf()
4823 for (i = 0; i < sd->glom_info.count; i++) { in sdstd_card_buf()
4824 bcopy(sd->glom_info.dma_buf_arr[i], in sdstd_card_buf()
4826 sd->glom_info.nbytes[i]); in sdstd_card_buf()
4827 offset += sd->glom_info.nbytes[i]; in sdstd_card_buf()
4834 blocksize = MIN(sd->client_block_size[func], nbytes); in sdstd_card_buf()
4847 if ((func == SDIO_FUNC_2) && (sd->glom_info.count != 0)) { in sdstd_card_buf()
4849 * requirements. So copying pkt to 4K aligned pre-allocated pkt. in sdstd_card_buf()
4850 * Total length should not cross the pre-alloced memory size in sdstd_card_buf()
4852 if (sd->txglom_mode == SDPCM_TXGLOM_CPY) { in sdstd_card_buf()
4854 for (i = 0; i < sd->glom_info.count; i++) { in sdstd_card_buf()
4855 bcopy(sd->glom_info.dma_buf_arr[i], in sdstd_card_buf()
4856 (uint8 *)sd->dma_buf + total_bytes, in sdstd_card_buf()
4857 sd->glom_info.nbytes[i]); in sdstd_card_buf()
4858 total_bytes += sd->glom_info.nbytes[i]; in sdstd_card_buf()
4865 bcopy(data, sd->dma_buf, nbytes); in sdstd_card_buf()
4871 cmd_arg = SFIELD(cmd_arg, CMD53_OP_CODE, 0); /* XXX SDIO spec v 1.10, Sec 5.3 */ in sdstd_card_buf()
4873 cmd_arg = SFIELD(cmd_arg, CMD53_OP_CODE, 1); /* XXX SDIO spec v 1.10, Sec 5.3 */ in sdstd_card_buf()
4882 sd->data_xfer_count = nbytes; in sdstd_card_buf()
4943 case -1: in sdstd_card_buf()
4947 case -2: in sdstd_card_buf()
4974 for (words = blocksize/4; words; words--) { in sdstd_card_buf()
4982 /* XXX in sdstd_card_buf()
5011 * SD_BufferDataPort0[0-15] | SD_BufferDataPort1[16-23] in sdstd_card_buf()
5042 case -1: in sdstd_card_buf()
5046 case -2: in sdstd_card_buf()
5067 sd->r_cnt, sd->t_cnt)); in sdstd_card_buf()
5077 /* XXX Step 14, Section 3.6.2.2 Stnd Cntrlr Spec */ in sdstd_card_buf()
5086 bcopy(sd->dma_buf, data, nbytes); in sdstd_card_buf()
5092 MFREE(sd->osh, localbuf, nbytes); in sdstd_card_buf()
5104 sd->client_block_size[func] = block_size; in set_client_block_size()
5122 /* Reset and re-initialize the device */
5139 si->sd_mode = SDIOH_MODE_SD1; in sdioh_sdio_reset()
5142 si->card_init_done = FALSE; in sdioh_sdio_reset()
5157 offset = sd->func_cis_ptr[func] + count; in cis_fetch()
5180 if ((sd->version == HOST_CONTR_VER_3) && sd_txglom) { in sd_map_dma()
5187 if ((va = DMA_ALLOC_CONSISTENT(sd->osh, dma_buf_size, SD_PAGE_BITS, &alloced, in sd_map_dma()
5188 &sd->dma_start_phys, 0x12)) == NULL) { in sd_map_dma()
5189 sd->sd_dma_mode = DMA_MODE_NONE; in sd_map_dma()
5190 sd->dma_start_buf = 0; in sd_map_dma()
5191 sd->dma_buf = (void *)0; in sd_map_dma()
5192 sd->dma_phys = 0; in sd_map_dma()
5193 sd->alloced_dma_size = 0; in sd_map_dma()
5196 sd->dma_start_buf = va; in sd_map_dma()
5197 sd->dma_buf = (void *)ROUNDUP((uintptr)va, SD_PAGE); in sd_map_dma()
5198 sd->dma_phys = ROUNDUP((sd->dma_start_phys), SD_PAGE); in sd_map_dma()
5199 sd->alloced_dma_size = alloced; in sd_map_dma()
5200 sd_err(("%s: Mapped DMA Buffer %dbytes @virt/phys: %p/0x%x-0x%x\n", in sd_map_dma()
5201 __FUNCTION__, sd->alloced_dma_size, sd->dma_buf, in sd_map_dma()
5202 (uint)PHYSADDRHI(sd->dma_phys), (uint)PHYSADDRLO(sd->dma_phys))); in sd_map_dma()
5206 if ((va = DMA_ALLOC_CONSISTENT(sd->osh, SD_PAGE, SD_PAGE_BITS, &alloced, in sd_map_dma()
5207 &sd->adma2_dscr_start_phys, 0x12)) == NULL) { in sd_map_dma()
5208 sd->sd_dma_mode = DMA_MODE_NONE; in sd_map_dma()
5209 sd->adma2_dscr_start_buf = 0; in sd_map_dma()
5210 sd->adma2_dscr_buf = (void *)0; in sd_map_dma()
5211 sd->adma2_dscr_phys = 0; in sd_map_dma()
5212 sd->alloced_adma2_dscr_size = 0; in sd_map_dma()
5216 sd->adma2_dscr_start_buf = va; in sd_map_dma()
5217 sd->adma2_dscr_buf = (void *)ROUNDUP((uintptr)va, SD_PAGE); in sd_map_dma()
5218 sd->adma2_dscr_phys = ROUNDUP((sd->adma2_dscr_start_phys), SD_PAGE); in sd_map_dma()
5219 sd->alloced_adma2_dscr_size = alloced; in sd_map_dma()
5220 sd_err(("%s: Mapped ADMA2 Descriptor Buffer %dbytes @virt/phys: %p/0x%x-0x%x\n", in sd_map_dma()
5221 __FUNCTION__, sd->alloced_adma2_dscr_size, sd->adma2_dscr_buf, in sd_map_dma()
5222 (uint)PHYSADDRHI(sd->adma2_dscr_phys), in sd_map_dma()
5223 (uint)PHYSADDRLO(sd->adma2_dscr_phys))); in sd_map_dma()
5231 if (sd->dma_start_buf) { in sd_unmap_dma()
5232 DMA_FREE_CONSISTENT(sd->osh, sd->dma_start_buf, sd->alloced_dma_size, in sd_unmap_dma()
5233 sd->dma_start_phys, 0x12); in sd_unmap_dma()
5236 if (sd->adma2_dscr_start_buf) { in sd_unmap_dma()
5237 DMA_FREE_CONSISTENT(sd->osh, sd->adma2_dscr_start_buf, sd->alloced_adma2_dscr_size, in sd_unmap_dma()
5238 sd->adma2_dscr_start_phys, 0x12); in sd_unmap_dma()
5245 bzero((char *)sd->adma2_dscr_buf, SD_PAGE); in sd_clear_adma_dscr_buf()
5252 memset((char *)sd->dma_buf, data, SD_PAGE); in sd_fill_dma_data_buf()
5262 adma2_dscr_table = sd->adma2_dscr_buf; in sd_create_adma_descriptor()
5263 adma1_dscr_table = sd->adma2_dscr_buf; in sd_create_adma_descriptor()
5265 switch (sd->sd_dma_mode) { in sd_create_adma_descriptor()
5290 sd_err(("%s: cannot create ADMA descriptor for DMA mode %d\n", in sd_create_adma_descriptor()
5291 __FUNCTION__, sd->sd_dma_mode)); in sd_create_adma_descriptor()
5305 ASSERT(sd->adma2_dscr_buf != NULL); in sd_dump_adma_dscr()
5307 adma2_dscr_table = sd->adma2_dscr_buf; in sd_dump_adma_dscr()
5308 adma1_dscr_table = sd->adma2_dscr_buf; in sd_dump_adma_dscr()
5310 switch (sd->sd_dma_mode) { in sd_dump_adma_dscr()
5312 sd_err(("ADMA2 Descriptor Table (%dbytes) @virt/phys: %p/0x%x-0x%x\n", in sd_dump_adma_dscr()
5313 SD_PAGE, sd->adma2_dscr_buf, in sd_dump_adma_dscr()
5314 (uint)PHYSADDRHI(sd->adma2_dscr_phys), in sd_dump_adma_dscr()
5315 (uint)PHYSADDRLO(sd->adma2_dscr_phys))); in sd_dump_adma_dscr()
5318 while (adma2_dscr_table->len_attr & ADMA2_ATTRIBUTE_VALID) { in sd_dump_adma_dscr()
5319 flags = adma2_dscr_table->len_attr & 0xFFFF; in sd_dump_adma_dscr()
5331 i, adma2_dscr_table, adma2_dscr_table->phys_addr, in sd_dump_adma_dscr()
5332 adma2_dscr_table->len_attr >> 16, flags, flags_str)); in sd_dump_adma_dscr()
5340 adma2_dscr_table->phys_addr); in sd_dump_adma_dscr()
5351 sd_err(("ADMA1 Descriptor Table (%dbytes) @virt/phys: %p/0x%x-0x%x\n", in sd_dump_adma_dscr()
5352 SD_PAGE, sd->adma2_dscr_buf, in sd_dump_adma_dscr()
5353 (uint)PHYSADDRHI(sd->adma2_dscr_phys), in sd_dump_adma_dscr()
5354 (uint)PHYSADDRLO(sd->adma2_dscr_phys))); in sd_dump_adma_dscr()
5357 for (i = 0; adma1_dscr_table->phys_addr_attr & ADMA2_ATTRIBUTE_VALID; i++) { in sd_dump_adma_dscr()
5358 flags = adma1_dscr_table->phys_addr_attr & 0x3F; in sd_dump_adma_dscr()
5371 adma1_dscr_table->phys_addr_attr & 0xFFFFF000, in sd_dump_adma_dscr()
5379 adma1_dscr_table->phys_addr_attr & 0xFFFFF000); in sd_dump_adma_dscr()