Lines Matching +full:0 +full:x104000
46 #define dcbf(p) { asm volatile("dc cvac, %0" : : "r"(p) : "memory"); }
62 #define IGB_TX_IEEE1588_TMST 0
98 IGB_RXQ_FLAG_LB_BSWAP_VLAN = 0x01,
123 uint8_t crc_len; /**< 0 if CRC stripped, 4 otherwise. */
124 uint8_t drop_en; /**< If not 0, set SRRCTL.Drop_En. */
134 IGB_CTX_0 = 0, /**< CTX0 */
157 #define TX_MACIP_LEN_CMP_MASK 0x000000000000FFFFULL /**< L2L3 header mask. */
158 #define TX_VLAN_CMP_MASK 0x00000000FFFF0000ULL /**< Vlan mask. */
159 #define TX_TCP_LEN_CMP_MASK 0x000000FF00000000ULL /**< TCP header mask. */
160 #define TX_TSO_MSS_CMP_MASK 0x00FFFF0000000000ULL /**< TSO segsz mask. */
212 #define rte_igb_prefetch(p) do {} while(0)
218 #define rte_packet_prefetch(p) do {} while(0)
271 tx_offload_mask.data = 0; in igbe_set_xmit_ctx()
272 type_tucmd_mlhl = 0; in igbe_set_xmit_ctx()
337 ctx_txd->u.seqnum_seed = 0; in igbe_set_xmit_ctx()
370 static const uint32_t l4_olinfo[2] = {0, E1000_ADVTXD_POPTS_TXSM}; in tx_desc_cksum_flags_to_olinfo()
371 static const uint32_t l3_olinfo[2] = {0, E1000_ADVTXD_POPTS_IXSM}; in tx_desc_cksum_flags_to_olinfo()
375 tmp |= l3_olinfo[(ol_flags & RTE_MBUF_F_TX_IP_CKSUM) != 0]; in tx_desc_cksum_flags_to_olinfo()
376 tmp |= l4_olinfo[(ol_flags & RTE_MBUF_F_TX_TCP_SEG) != 0]; in tx_desc_cksum_flags_to_olinfo()
384 static uint32_t vlan_cmd[2] = {0, E1000_ADVTXD_DCMD_VLE}; in tx_desc_vlan_flags_to_cmdtype()
385 static uint32_t tso_cmd[2] = {0, E1000_ADVTXD_DCMD_TSE}; in tx_desc_vlan_flags_to_cmdtype()
386 cmdtype = vlan_cmd[(ol_flags & RTE_MBUF_F_TX_VLAN) != 0]; in tx_desc_vlan_flags_to_cmdtype()
387 cmdtype |= tso_cmd[(ol_flags & RTE_MBUF_F_TX_TCP_SEG) != 0]; in tx_desc_vlan_flags_to_cmdtype()
413 uint32_t new_ctx = 0; in eth_igb_xmit_pkts()
414 uint32_t ctx = 0; in eth_igb_xmit_pkts()
415 union igb_tx_offload tx_offload = {0}; in eth_igb_xmit_pkts()
424 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) { in eth_igb_xmit_pkts()
516 if (nb_tx == 0) in eth_igb_xmit_pkts()
517 return 0; in eth_igb_xmit_pkts()
592 for (int i = 0; i < m_seg->data_len; i += 64) { in eth_igb_xmit_pkts()
647 for (i = 0; i < nb_pkts; i++) { in eth_igb_prep_pkts()
666 if (ret != 0) { in eth_igb_prep_pkts()
672 if (ret != 0) { in eth_igb_prep_pkts()
686 #define IGB_PACKET_TYPE_IPV4 0X01
687 #define IGB_PACKET_TYPE_IPV4_TCP 0X11
688 #define IGB_PACKET_TYPE_IPV4_UDP 0X21
689 #define IGB_PACKET_TYPE_IPV4_SCTP 0X41
690 #define IGB_PACKET_TYPE_IPV4_EXT 0X03
691 #define IGB_PACKET_TYPE_IPV4_EXT_SCTP 0X43
692 #define IGB_PACKET_TYPE_IPV6 0X04
693 #define IGB_PACKET_TYPE_IPV6_TCP 0X14
694 #define IGB_PACKET_TYPE_IPV6_UDP 0X24
695 #define IGB_PACKET_TYPE_IPV6_EXT 0X0C
696 #define IGB_PACKET_TYPE_IPV6_EXT_TCP 0X1C
697 #define IGB_PACKET_TYPE_IPV6_EXT_UDP 0X2C
698 #define IGB_PACKET_TYPE_IPV4_IPV6 0X05
699 #define IGB_PACKET_TYPE_IPV4_IPV6_TCP 0X15
700 #define IGB_PACKET_TYPE_IPV4_IPV6_UDP 0X25
701 #define IGB_PACKET_TYPE_IPV4_IPV6_EXT 0X0D
702 #define IGB_PACKET_TYPE_IPV4_IPV6_EXT_TCP 0X1D
703 #define IGB_PACKET_TYPE_IPV4_IPV6_EXT_UDP 0X2D
704 #define IGB_PACKET_TYPE_MAX 0X80
705 #define IGB_PACKET_TYPE_MASK 0X7F
706 #define IGB_PACKET_TYPE_SHIFT 0X04
766 uint64_t pkt_flags = ((hl_tp_rs & 0x0F) == 0) ? 0 : RTE_MBUF_F_RX_RSS_HASH; in rx_desc_hlen_type_rss_to_pkt_flags()
770 0, 0, 0, RTE_MBUF_F_RX_IEEE1588_PTP, in rx_desc_hlen_type_rss_to_pkt_flags()
771 0, 0, 0, 0, in rx_desc_hlen_type_rss_to_pkt_flags()
777 /* EtherType is in bits 8:10 in Packet Type, and not in the default 0:2 */ in rx_desc_hlen_type_rss_to_pkt_flags()
779 pkt_flags |= ip_pkt_etqf_map[(hl_tp_rs >> 12) & 0x07]; in rx_desc_hlen_type_rss_to_pkt_flags()
781 pkt_flags |= ip_pkt_etqf_map[(hl_tp_rs >> 4) & 0x07]; in rx_desc_hlen_type_rss_to_pkt_flags()
796 RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED : 0); in rx_desc_status_to_pkt_flags()
844 nb_rx = 0; in eth_igb_recv_pkts()
845 nb_hold = 0; in eth_igb_recv_pkts()
892 "staterr=0x%x pkt_len=%u", in eth_igb_recv_pkts()
910 rx_id = 0; in eth_igb_recv_pkts()
920 if ((rx_id & 0x3) == 0) { in eth_igb_recv_pkts()
929 rxdp->read.hdr_addr = 0; in eth_igb_recv_pkts()
999 rx_id = (uint16_t) ((rx_id == 0) ? in eth_igb_recv_pkts()
1002 nb_hold = 0; in eth_igb_recv_pkts()
1031 nb_rx = 0; in eth_igb_recv_scattered_pkts()
1032 nb_hold = 0; in eth_igb_recv_scattered_pkts()
1083 "staterr=0x%x data_len=%u", in eth_igb_recv_scattered_pkts()
1101 rx_id = 0; in eth_igb_recv_scattered_pkts()
1111 if ((rx_id & 0x3) == 0) { in eth_igb_recv_scattered_pkts()
1124 rxdp->read.hdr_addr = 0; in eth_igb_recv_scattered_pkts()
1172 if (unlikely(rxq->crc_len > 0)) { in eth_igb_recv_scattered_pkts()
1261 rx_id = (uint16_t) ((rx_id == 0) ? in eth_igb_recv_scattered_pkts()
1264 nb_hold = 0; in eth_igb_recv_scattered_pkts()
1275 * (num_ring_desc * sizeof(struct e1000_rx/tx_desc)) % 128 == 0
1284 for (i = 0; i < txq->nb_tx_desc; i++) { in igb_tx_queue_release_mbufs()
1319 int count = 0; in igb_tx_done_cleanup()
1400 if (likely(tx_id == tx_first && count != 0)) in igb_tx_done_cleanup()
1433 txq->tx_head = 0; in igb_reset_tx_queue_stat()
1434 txq->tx_tail = 0; in igb_reset_tx_queue_stat()
1435 txq->ctx_curr = 0; in igb_reset_tx_queue_stat()
1436 memset((void*)&txq->ctx_cache, 0, in igb_reset_tx_queue_stat()
1443 static const union e1000_adv_tx_desc zeroed_desc = {{0}}; in igb_reset_tx_queue()
1450 for (i = 0; i < txq->nb_tx_desc; i++) { in igb_reset_tx_queue()
1456 for (i = 0; i < txq->nb_tx_desc; i++) { in igb_reset_tx_queue()
1524 if (nb_desc % IGB_TXD_ALIGN != 0 || in eth_igb_tx_queue_setup()
1534 if (tx_conf->tx_free_thresh != 0) in eth_igb_tx_queue_setup()
1537 if (tx_conf->tx_rs_thresh != 0) in eth_igb_tx_queue_setup()
1540 if (tx_conf->tx_thresh.wthresh == 0 && hw->mac.type != e1000_82576) in eth_igb_tx_queue_setup()
1575 if (txq->wthresh > 0 && hw->mac.type == e1000_82576) in eth_igb_tx_queue_setup()
1578 txq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ? in eth_igb_tx_queue_setup()
1587 index = ((uint64_t)hw->hw_addr - base_hw_addr) / 0x104000; in eth_igb_tx_queue_setup()
1590 printf("hw tx ring size: %d:%ld[0x%lx:%p]\n", in eth_igb_tx_queue_setup()
1604 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64, in eth_igb_tx_queue_setup()
1613 return 0; in eth_igb_tx_queue_setup()
1622 for (i = 0; i < rxq->nb_rx_desc; i++) { in igb_rx_queue_release_mbufs()
1651 static const union e1000_adv_rx_desc zeroed_desc = {{0}}; in igb_reset_rx_queue()
1655 for (i = 0; i < rxq->nb_rx_desc; i++) { in igb_reset_rx_queue()
1659 rxq->rx_tail = 0; in igb_reset_rx_queue()
1705 rx_queue_offload_capa = 0; in igb_get_rx_queue_offloads_capa()
1734 if (nb_desc % IGB_RXD_ALIGN != 0 || in eth_igb_rx_queue_setup()
1757 if (rxq->wthresh > 0 && in eth_igb_rx_queue_setup()
1763 rxq->reg_idx = (uint16_t)((RTE_ETH_DEV_SRIOV(dev).active == 0) ? in eth_igb_rx_queue_setup()
1769 rxq->crc_len = 0; in eth_igb_rx_queue_setup()
1790 index = ((uint64_t)hw->hw_addr - base_hw_addr) / 0x104000; in eth_igb_rx_queue_setup()
1793 printf("hw rx ring size: %d:%ld[0x%lx:%p]\n", in eth_igb_rx_queue_setup()
1807 PMD_INIT_LOG(DEBUG, "sw_ring=%p hw_ring=%p dma_addr=0x%"PRIx64, in eth_igb_rx_queue_setup()
1813 return 0; in eth_igb_rx_queue_setup()
1822 uint32_t desc = 0; in eth_igb_rx_queue_count()
1891 for (i = 0; i < dev->data->nb_tx_queues; i++) { in igb_dev_clear_queues()
1899 for (i = 0; i < dev->data->nb_rx_queues; i++) { in igb_dev_clear_queues()
1913 for (i = 0; i < dev->data->nb_rx_queues; i++) { in igb_dev_free_queues()
1917 dev->data->nb_rx_queues = 0; in igb_dev_free_queues()
1919 for (i = 0; i < dev->data->nb_tx_queues; i++) { in igb_dev_free_queues()
1923 dev->data->nb_tx_queues = 0; in igb_dev_free_queues()
1949 0x6D, 0x5A, 0x56, 0xDA, 0x25, 0x5B, 0x0E, 0xC2,
1950 0x41, 0x67, 0x25, 0x3D, 0x43, 0xA3, 0x8F, 0xB0,
1951 0xD0, 0xCA, 0x2B, 0xCB, 0xAE, 0x7B, 0x30, 0xB4,
1952 0x77, 0xCB, 0x2D, 0xA3, 0x80, 0x30, 0xF2, 0x0C,
1953 0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA,
1980 for (i = 0; i < 10; i++) { in igb_hw_rss_hash_set()
1985 E1000_WRITE_REG_ARRAY(hw, E1000_RSSRK(0), i, rss_key); in igb_hw_rss_hash_set()
2032 if (rss_hf != 0) /* Enable RSS */ in eth_igb_rss_hash_update()
2034 return 0; /* Nothing to do */ in eth_igb_rss_hash_update()
2037 if (rss_hf == 0) /* Disable RSS */ in eth_igb_rss_hash_update()
2040 return 0; in eth_igb_rss_hash_update()
2057 for (i = 0; i < 10; i++) { in eth_igb_rss_hash_conf_get()
2058 rss_key = E1000_READ_REG_ARRAY(hw, E1000_RSSRK(0), i); in eth_igb_rss_hash_conf_get()
2059 hash_key[(i * 4)] = rss_key & 0x000000FF; in eth_igb_rss_hash_conf_get()
2060 hash_key[(i * 4) + 1] = (rss_key >> 8) & 0x000000FF; in eth_igb_rss_hash_conf_get()
2061 hash_key[(i * 4) + 2] = (rss_key >> 16) & 0x000000FF; in eth_igb_rss_hash_conf_get()
2062 hash_key[(i * 4) + 3] = (rss_key >> 24) & 0x000000FF; in eth_igb_rss_hash_conf_get()
2068 if ((mrqc & E1000_MRQC_ENABLE_RSS_4Q) == 0) { /* RSS is disabled */ in eth_igb_rss_hash_conf_get()
2069 rss_conf->rss_hf = 0; in eth_igb_rss_hash_conf_get()
2070 return 0; in eth_igb_rss_hash_conf_get()
2072 rss_hf = 0; in eth_igb_rss_hash_conf_get()
2092 return 0; in eth_igb_rss_hash_conf_get()
2106 shift = (hw->mac.type == e1000_82575) ? 6 : 0; in igb_rss_configure()
2107 for (i = 0; i < 128; i++) { in igb_rss_configure()
2115 i % dev->data->nb_rx_queues : 0); in igb_rss_configure()
2126 if ((rss_conf.rss_hf & IGB_RSS_OFFLOAD_ALL) == 0) { in igb_rss_configure()
2137 * Return 1 if it supports, otherwise, return 0.
2166 return 0; in igb_is_vmdq_supported()
2183 /* Check if mac type can support VMDq, return value of 0 means NOT support */ in igb_vmdq_rx_hw_configure()
2184 if (igb_is_vmdq_supported(dev) == 0) in igb_vmdq_rx_hw_configure()
2206 for (i = 0; i < E1000_VMOLR_SIZE; i++) { in igb_vmdq_rx_hw_configure()
2231 for (i = 0; i < E1000_VMOLR_SIZE; i++) { in igb_vmdq_rx_hw_configure()
2239 for (i = 0; i < IGB_VFTA_SIZE; i++) in igb_vmdq_rx_hw_configure()
2248 * In this case, all pools should be able to read from mac addr 0 in igb_vmdq_rx_hw_configure()
2250 E1000_WRITE_REG(hw, E1000_RAH(0), (E1000_RAH_AV | UINT16_MAX)); in igb_vmdq_rx_hw_configure()
2251 E1000_WRITE_REG(hw, E1000_RAL(0), UINT32_MAX); in igb_vmdq_rx_hw_configure()
2254 for (i = 0; i < cfg->nb_pool_maps; i++) { in igb_vmdq_rx_hw_configure()
2264 return 0; in igb_vmdq_rx_hw_configure()
2282 for (i = 0; i < rxq->nb_rx_desc; i++) { in igb_alloc_rx_queue_mbufs()
2294 rxd->read.hdr_addr = 0; in igb_alloc_rx_queue_mbufs()
2299 return 0; in igb_alloc_rx_queue_mbufs()
2317 mrqc |= 0x3 << E1000_MRQC_DEF_Q_SHIFT; in igb_dev_mq_rx_configure()
2319 } else if(RTE_ETH_DEV_SRIOV(dev).active == 0) { in igb_dev_mq_rx_configure()
2339 return 0; in igb_dev_mq_rx_configure()
2358 srrctl = 0; in eth_igb_rx_init()
2388 rctl_bsize = 0; in eth_igb_rx_init()
2390 for (i = 0; i < dev->data->nb_rx_queues; i++) { in eth_igb_rx_init()
2396 rxq->flags = 0; in eth_igb_rx_init()
2419 rxq->crc_len = 0; in eth_igb_rx_init()
2441 * If this field is equal to 0b, then RCTL.BSIZE in eth_igb_rx_init()
2462 if ((rctl_bsize == 0) || (rctl_bsize > buf_size)) in eth_igb_rx_init()
2479 rxdctl &= 0xFFF00000; in eth_igb_rx_init()
2480 rxdctl |= (rxq->pthresh & 0x1F); in eth_igb_rx_init()
2481 rxdctl |= ((rxq->hthresh & 0x1F) << 8); in eth_igb_rx_init()
2482 rxdctl |= ((rxq->wthresh & 0x1F) << 16); in eth_igb_rx_init()
2507 if (rctl_bsize > 0) { in eth_igb_rx_init()
2555 for (i = 0; i < dev->data->nb_rx_queues; i++) { in eth_igb_rx_init()
2571 for (i = 0; i < dev->data->nb_rx_queues; i++) { in eth_igb_rx_init()
2599 for (i = 0; i < dev->data->nb_rx_queues; i++) { in eth_igb_rx_init()
2601 E1000_WRITE_REG(hw, E1000_RDH(rxq->reg_idx), 0); in eth_igb_rx_init()
2605 return 0; in eth_igb_rx_init()
2625 for (i = 0; i < dev->data->nb_tx_queues; i++) { in eth_igb_tx_init()
2638 E1000_WRITE_REG(hw, E1000_TDT(txq->reg_idx), 0); in eth_igb_tx_init()
2639 E1000_WRITE_REG(hw, E1000_TDH(txq->reg_idx), 0); in eth_igb_tx_init()
2643 txdctl |= txq->pthresh & 0x1F; in eth_igb_tx_init()
2644 txdctl |= ((txq->hthresh & 0x1F) << 8); in eth_igb_tx_init()
2645 txdctl |= ((txq->wthresh & 0x1F) << 16); in eth_igb_tx_init()
2686 rctl_bsize = 0; in eth_igbvf_rx_init()
2688 for (i = 0; i < dev->data->nb_rx_queues; i++) { in eth_igbvf_rx_init()
2694 rxq->flags = 0; in eth_igbvf_rx_init()
2730 * If this field is equal to 0b, then RCTL.BSIZE in eth_igbvf_rx_init()
2751 if ((rctl_bsize == 0) || (rctl_bsize > buf_size)) in eth_igbvf_rx_init()
2768 rxdctl &= 0xFFF00000; in eth_igbvf_rx_init()
2769 rxdctl |= (rxq->pthresh & 0x1F); in eth_igbvf_rx_init()
2770 rxdctl |= ((rxq->hthresh & 0x1F) << 8); in eth_igbvf_rx_init()
2777 rxdctl |= 0x10000; in eth_igbvf_rx_init()
2781 rxdctl |= ((rxq->wthresh & 0x1F) << 16); in eth_igbvf_rx_init()
2796 for (i = 0; i < dev->data->nb_rx_queues; i++) { in eth_igbvf_rx_init()
2798 E1000_WRITE_REG(hw, E1000_RDH(i), 0); in eth_igbvf_rx_init()
2802 return 0; in eth_igbvf_rx_init()
2821 for (i = 0; i < dev->data->nb_tx_queues; i++) { in eth_igbvf_tx_init()
2834 E1000_WRITE_REG(hw, E1000_TDT(i), 0); in eth_igbvf_tx_init()
2835 E1000_WRITE_REG(hw, E1000_TDH(i), 0); in eth_igbvf_tx_init()
2839 txdctl |= txq->pthresh & 0x1F; in eth_igbvf_tx_init()
2840 txdctl |= ((txq->hthresh & 0x1F) << 8); in eth_igbvf_tx_init()
2847 txdctl |= 0x10000; in eth_igbvf_tx_init()
2851 txdctl |= ((txq->wthresh & 0x1F) << 16); in eth_igbvf_tx_init()
2914 return 0; in igb_rss_conf_init()
2953 memset(&filter_info->rss_info, 0, in igb_config_rss_filter()
2955 return 0; in igb_config_rss_filter()
2964 shift = (hw->mac.type == e1000_82575) ? 6 : 0; in igb_config_rss_filter()
2965 for (i = 0, j = 0; i < 128; i++, j++) { in igb_config_rss_filter()
2973 j = 0; in igb_config_rss_filter()
2983 if ((rss_conf.rss_hf & IGB_RSS_OFFLOAD_ALL) == 0) { in igb_config_rss_filter()
2985 return 0; in igb_config_rss_filter()
2994 return 0; in igb_config_rss_filter()