Lines Matching +full:0 +full:x41c00000
38 reg = < 0x80000000 0x4000000 >;
46 linux,stdout-path = "/axi@0/serial@40600000";
50 #cpus = <0x1>;
51 #size-cells = <0>;
52 microblaze_0: cpu@0 {
55 d-cache-baseaddr = <0x80000000>;
56 d-cache-highaddr = <0x83ffffff>;
57 d-cache-line-size = <0x10>;
58 d-cache-size = <0x2000>;
60 i-cache-baseaddr = <0x80000000>;
61 i-cache-highaddr = <0x83ffffff>;
62 i-cache-line-size = <0x10>;
63 i-cache-size = <0x2000>;
65 reg = <0>;
67 xlnx,addr-tag-bits = <0xd>;
68 xlnx,allow-dcache-wr = <0x1>;
69 xlnx,allow-icache-wr = <0x1>;
70 xlnx,area-optimized = <0x0>;
71 xlnx,avoid-primitives = <0x0>;
72 xlnx,branch-target-cache-size = <0x0>;
73 xlnx,cache-byte-size = <0x2000>;
74 xlnx,d-axi = <0x1>;
75 xlnx,d-lmb = <0x1>;
76 xlnx,d-plb = <0x0>;
77 xlnx,data-size = <0x20>;
78 xlnx,dcache-addr-tag = <0xd>;
79 xlnx,dcache-always-used = <0x1>;
80 xlnx,dcache-byte-size = <0x2000>;
81 xlnx,dcache-data-width = <0x0>;
82 xlnx,dcache-force-tag-lutram = <0x0>;
83 xlnx,dcache-interface = <0x0>;
84 xlnx,dcache-line-len = <0x4>;
85 xlnx,dcache-use-fsl = <0x0>;
86 xlnx,dcache-use-writeback = <0x0>;
87 xlnx,dcache-victims = <0x0>;
88 xlnx,debug-enabled = <0x1>;
89 xlnx,div-zero-exception = <0x0>;
90 xlnx,dynamic-bus-sizing = <0x1>;
91 xlnx,ecc-use-ce-exception = <0x0>;
92 xlnx,edge-is-positive = <0x1>;
93 xlnx,endianness = <0x1>;
95 xlnx,fault-tolerant = <0x0>;
96 xlnx,fpu-exception = <0x0>;
97 xlnx,freq = <0x3f940ab>;
98 xlnx,fsl-data-size = <0x20>;
99 xlnx,fsl-exception = <0x0>;
100 xlnx,fsl-links = <0x0>;
101 xlnx,i-axi = <0x0>;
102 xlnx,i-lmb = <0x1>;
103 xlnx,i-plb = <0x0>;
104 xlnx,icache-always-used = <0x1>;
105 xlnx,icache-data-width = <0x0>;
106 xlnx,icache-force-tag-lutram = <0x0>;
107 xlnx,icache-interface = <0x0>;
108 xlnx,icache-line-len = <0x4>;
109 xlnx,icache-streams = <0x0>;
110 xlnx,icache-use-fsl = <0x0>;
111 xlnx,icache-victims = <0x0>;
112 xlnx,ill-opcode-exception = <0x0>;
114 xlnx,interconnect = <0x2>;
115 xlnx,interconnect-m-axi-dc-aw-register = <0x0>;
116 xlnx,interconnect-m-axi-dc-read-issuing = <0x2>;
117 xlnx,interconnect-m-axi-dc-w-register = <0x0>;
118 xlnx,interconnect-m-axi-dc-write-issuing = <0x20>;
119 xlnx,interconnect-m-axi-dp-read-issuing = <0x1>;
120 xlnx,interconnect-m-axi-dp-write-issuing = <0x1>;
121 xlnx,interconnect-m-axi-ic-read-issuing = <0x2>;
122 xlnx,interconnect-m-axi-ip-read-issuing = <0x1>;
123 xlnx,interrupt-is-edge = <0x0>;
124 xlnx,lockstep-slave = <0x0>;
125 xlnx,mmu-dtlb-size = <0x1>;
126 xlnx,mmu-itlb-size = <0x1>;
127 xlnx,mmu-privileged-instr = <0x0>;
128 xlnx,mmu-tlb-access = <0x3>;
129 xlnx,mmu-zones = <0x2>;
130 xlnx,number-of-pc-brk = <0x1>;
131 xlnx,number-of-rd-addr-brk = <0x0>;
132 xlnx,number-of-wr-addr-brk = <0x0>;
133 xlnx,opcode-0x0-illegal = <0x0>;
134 xlnx,optimization = <0x0>;
135 xlnx,pvr = <0x0>;
136 xlnx,pvr-user1 = <0x0>;
137 xlnx,pvr-user2 = <0x0>;
138 xlnx,reset-msr = <0x0>;
139 xlnx,sco = <0x0>;
140 xlnx,stream-interconnect = <0x0>;
141 xlnx,unaligned-exceptions = <0x0>;
142 xlnx,use-barrel = <0x1>;
143 xlnx,use-branch-target-cache = <0x0>;
144 xlnx,use-dcache = <0x1>;
145 xlnx,use-div = <0x0>;
146 xlnx,use-ext-brk = <0x1>;
147 xlnx,use-ext-nm-brk = <0x1>;
148 xlnx,use-extended-fsl-instr = <0x0>;
149 xlnx,use-fpu = <0x0>;
150 xlnx,use-hw-mul = <0x1>;
151 xlnx,use-icache = <0x1>;
152 xlnx,use-interrupt = <0x1>;
153 xlnx,use-mmu = <0x3>;
154 xlnx,use-msr-instr = <0x1>;
155 xlnx,use-pcmp-instr = <0x0>;
156 xlnx,use-stack-protection = <0x0>;
159 axi4lite_0: axi@0 {
168 interrupts = < 2 0 >;
169 local-mac-address = [ 00 0a 35 aa de 00 ];
171 reg = < 0x40e00000 0x10000 >;
172 xlnx,duplex = <0x1>;
174 xlnx,include-global-buffers = <0x0>;
175 xlnx,include-internal-loopback = <0x0>;
176 xlnx,include-mdio = <0x1>;
177 xlnx,include-phy-constraints = <0x1>;
178 xlnx,interconnect-s-axi-read-acceptance = <0x1>;
179 xlnx,interconnect-s-axi-write-acceptance = <0x1>;
180 xlnx,rx-ping-pong = <0x0>;
181 xlnx,s-axi-aclk-period-ps = <0x3a98>;
182 xlnx,s-axi-id-width = <0x1>;
183 xlnx,s-axi-supports-narrow-burst = <0x0>;
184 xlnx,tx-ping-pong = <0x0>;
188 #size-cells = <0>;
201 reg = < 0x40a00000 0x10000 >;
203 xlnx,fifo-exist = <0x1>;
204 xlnx,num-ss-bits = <0x1>;
205 xlnx,num-transfer-bits = <0x8>;
206 xlnx,sck-ratio = <0x4>;
214 interrupts = < 3 0 >;
215 port-number = <0>;
216 reg = < 0x40600000 0x10000 >;
217 xlnx,baudrate = <0x1c200>;
218 xlnx,data-bits = <0x8>;
220 xlnx,odd-parity = <0x1>;
221 xlnx,s-axi-aclk-freq-hz = <0x3f940ab>;
222 xlnx,use-parity = <0x0>;
225 #interrupt-cells = <0x2>;
228 reg = < 0x41200000 0x10000 >;
229 xlnx,kind-of-intr = <0xc>;
230 xlnx,num-intr-inputs = <0x4>;
236 interrupts = < 0 2 >;
237 reg = < 0x41c00000 0x10000 >;
238 xlnx,count-width = <0x20>;
240 xlnx,gen0-assert = <0x1>;
241 xlnx,gen1-assert = <0x1>;
242 xlnx,one-timer-only = <0x0>;
243 xlnx,trig0-assert = <0x1>;
244 xlnx,trig1-assert = <0x1>;