plat: rk3399: set pmu-m0 sram addr

Change-Id: Ic77ee127fba7f1710849fe0057ec6b20f2aaa08a
Signed-off-by: Shengfei xu <xsf@rock-chips.com>

rk3399: ddr: update ddr init bin v1.07

1.fix SOC side vref value calculation error.
2.remove RX offset calibration
3.override write leveling value to 0x200 and disable read leveling.
4.disable read

rk3399: ddr: update ddr init bin v1.07

1.fix SOC side vref value calculation error.
2.remove RX offset calibration
3.override write leveling value to 0x200 and disable read leveling.
4.disable read leveling.

Change-Id: Ic825c3bd591be050238c7a97efcaa40b6dd57a86
Signed-off-by: YouMin Chen <cym@rock-chips.com>

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plat:rk3399: rockchip: add support save/restore configuration for DDR during enter S3

This patch intend to support save the registers of the DDR controller
and PHY before suspend, and restore them a

plat:rk3399: rockchip: add support save/restore configuration for DDR during enter S3

This patch intend to support save the registers of the DDR controller
and PHY before suspend, and restore them after resume.

Change-Id: Ia2cc6664baa4116be4587e6ad3023ce325270fc0
Signed-off-by: Shengfei xu <xsf@rock-chips.com>

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RK322x: Trust: update optee version to v1.6

fix some system suspend/resume issues

Change-Id: I0c67ed58398c9c189e54be7a32ca2dd11a632c38
Signed-off-by: Jianhong Chen <chenjh@rock-chips.com>

rkplat: rk3399:pd_sdioaudio power down disable, when suspend.

Change-Id: I3778818ffc20301e42bf632b2b8a712c261883bb
Signed-off-by: Shengfei xu <xsf@rock-chips.com>

rkplat: rk3399: enable M0, when sleep

1. recode sram lds
2. move pmu_ddr_suspend code into sram

Change-Id: I7d10ae80365f2cba59a16a23748a71acec1a3aee
Signed-off-by: Shengfei xu <xsf@rock-chips.com>

rk3399: ddr: update ddr init bin version to v1.06

config noc timing of readlatency to 0x80.

Change-Id: I5dc95eaa99f151818e231aecfc4b2bf637ecfbaa
Signed-off-by: Tang Yun ping <typ@rock-chips.com>

rkplat: rk3399:slove the system time error, when suspen/resume.

Fix error define for TIMER_DIS, fix to 0x0

Change-Id: I7d25f496a7dc897abd27b6d26b47a5f322e64e15
Signed-off-by: Shengfei xu <xsf@rock-

rkplat: rk3399:slove the system time error, when suspen/resume.

Fix error define for TIMER_DIS, fix to 0x0

Change-Id: I7d25f496a7dc897abd27b6d26b47a5f322e64e15
Signed-off-by: Shengfei xu <xsf@rock-chips.com>

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px5: update PX5MINIALL.ini version

Change-Id: I8c163744bb79f9c3ff14c90316a6eff9831f4786
Signed-off-by: Jason Song <sxj@rock-chips.com>

rk3368: bl31 v1.8: set uart print port dynamiclly and dump wakeup irq

Change-Id: I60ea8a324083806d91e508fa001e6cf0613fac69
Signed-off-by: Jianhong Chen <chenjh@rock-chips.com>

rk3399: bl31: fix suspend issue during ddr changing frequency

To fix suspend issue during ddr changing frequency, build based on
the commit of arm-trusted-firmware:
6b958c9c6fced39be0e86ccbbc5aa61ae

rk3399: bl31: fix suspend issue during ddr changing frequency

To fix suspend issue during ddr changing frequency, build based on
the commit of arm-trusted-firmware:
6b958c9c6fced39be0e86ccbbc5aa61aef8b3315

Change-Id: Ib1df36e4a706a782262b9ad24c8f5c12c74e751c
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

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rk322x: MiniLoader update to V2.32

Support soft sign 1024bits RSA key only

Change-Id: Ie1e9aaf6cbe362e1c9e4739ce44bd2548b97bd59
Signed-off-by: William Zhang <william.zhang@rock-chips.com>

px5: add init config for px5 chip.

compile cmd:

make px5_defconfig
make ARCHV=aarch64

ini, must modify this two file:

tools/rk_tools/RKBOOT/PX5MINIALL.ini
tools/rk_tools/RKTRUST/PX5TRUST.ini

Cha

px5: add init config for px5 chip.

compile cmd:

make px5_defconfig
make ARCHV=aarch64

ini, must modify this two file:

tools/rk_tools/RKBOOT/PX5MINIALL.ini
tools/rk_tools/RKTRUST/PX5TRUST.ini

Change-Id: I81250ebc3b49b59cff64a05f86d7ed19a13a6a7d
Signed-off-by: Jason Song <sxj@rock-chips.com>

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rk3399: To support ddr frequency scaling function.

Fix suspend fail when ddr change frequency.

Change-Id: I6dacad08c080af1982dc6d860a97b5d0128ac14b
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>

rk3368: bl31 v1.8: enable pmu pvtm clk and add sip for px5

Change-Id: I548aebae1eba64e9655fd4e547450e2a77196c8c
Signed-off-by: Jianhong Chen <chenjh@rock-chips.com>

rk3399: ddr: update ddr init bin version to v1.05

Amend msch ddrconfig register write error and make sure row numbers
configure in msch is equal to row numbers configure in ddr controller

Change-Id

rk3399: ddr: update ddr init bin version to v1.05

Amend msch ddrconfig register write error and make sure row numbers
configure in msch is equal to row numbers configure in ddr controller

Change-Id: I03f673075ffc68f177a65e08a50896144eda1b4b
Signed-off-by: Tang Yun ping <typ@rock-chips.com>

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RK322x: Trust: update optee version to v1.5

sleep: add pmic_sleep pin control for pmic

Change-Id: Ib65c99f28e804acee4c187efac9558c3f8a7892a
Signed-off-by: Jianhong Chen <chenjh@rock-chips.com>

rk3368: bl31.bin update version to v1.8

bl31 support PX5 from v1.8

Change-Id: I0ee4efda44ab520d1aae8b000955589fa9d7799f
Signed-off-by: Jianhong Chen <chenjh@rock-chips.com>

rk3368: ddr: ddr init code update to v1.18

ddr init code update to v1.18 to supporting px5

Change-Id: I7b00188711d08c735809376a0511cd728566f30c
Signed-off-by: Tang Yun ping <typ@rock-chips.com>

3368:minloader: add PX5 support

Change-Id: Ifd2cf9ab71176a9a22fcbe05e34c5a623ac0eacf
Signed-off-by: chenfen <chenfen@rock-chips.com>

RK3288: DDR: DDR Version 1.01 20160803

All DRAM type init frequency increase to 400MHz,
because some type of screen display gilitter before
kernel set DDR rate to high frequency.

Change-Id: I519b60

RK3288: DDR: DDR Version 1.01 20160803

All DRAM type init frequency increase to 400MHz,
because some type of screen display gilitter before
kernel set DDR rate to high frequency.

Change-Id: I519b606db92e10ae6807efecf361fe2379cbf28d
Signed-off-by: Hecanyang <hcy@rock-chips.com>

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rk3399 miniloader change upgrade flag for charge

Change-Id: I80a4865771e930b1e88825c351f547a46e8ca6d3
Signed-off-by: chenfen <chenfen@rock-chips.com>

rkplat: rk3399: pwm wakeup enable

Change-Id: I6a174bbb988675551a56bb456d905a22a0ab7f3c
Signed-off-by: Shengfei xu <xsf@rock-chips.com>

RK3399: ddr: update ddr init bin version to v1.04

1. enable lpddr4 mask write
2. support only one channel

Change-Id: I64eec491abb35203d8055c8dffa111bcfdb1a710
Signed-off-by: Hecanyang <hcy@rock-chi

RK3399: ddr: update ddr init bin version to v1.04

1. enable lpddr4 mask write
2. support only one channel

Change-Id: I64eec491abb35203d8055c8dffa111bcfdb1a710
Signed-off-by: Hecanyang <hcy@rock-chips.com>

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RK3399: ddr: update ddr init bin version to v1.03

1. support lpddr4.
2. ajdust phy vref value when enable soc odt.

Change-Id: I8ea02f6079c487f75f513fb3db7677d4550d485b
Signed-off-by: Tang Yun ping

RK3399: ddr: update ddr init bin version to v1.03

1. support lpddr4.
2. ajdust phy vref value when enable soc odt.

Change-Id: I8ea02f6079c487f75f513fb3db7677d4550d485b
Signed-off-by: Tang Yun ping <typ@rock-chips.com>

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