| 07ada3e8 | 01-Jun-2021 |
Jon Lin <jon.lin@rock-chips.com> |
rk356x: loader: update version to v1.09
from commit: b651e66 src: spinand: Support new devices
Change-Id: I089c9ad80fa357612fa42fd7e23f50fd818c997f Signed-off-by: Jon Lin <jon.lin@rock-chips.com> |
| f75c4968 | 09-Jun-2021 |
XiaoDong Huang <derrick.huang@rock-chips.com> |
rk1808: bl31: update version to v1.14
Build from ATF commit: 4adcfc013 plat: rk1808: fix error of compillig with "DEBUG=0" option update feature: 4adcfc013 plat: rk1808: fix error of compill
rk1808: bl31: update version to v1.14
Build from ATF commit: 4adcfc013 plat: rk1808: fix error of compillig with "DEBUG=0" option update feature: 4adcfc013 plat: rk1808: fix error of compillig with "DEBUG=0" option d1cc80aa8 plat: rockchip: common: fix the min tWR overflow 9084aeaec plat: rk1808: remove dsmpd when pll setting 3e4fd0740 rockchip: workaround for gicv3 secure bug 857e9c1b4 rockchip: fix err of parsing ddr_parameter 5603427d7 plat: rk1808: ddr: fix the error about DDR4 DLL 2041b46d8 BACKPORT: Prevent speculative execution past ERET
Change-Id: Ia56aed48f8a67dc4909dcb695b2ae70b37489995 Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
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| 4f2eb7ae | 08-Jun-2021 |
XiaoDong Huang <derrick.huang@rock-chips.com> |
rv1126: tee with ta: update version to v1.18
Build from optee commit in develop-next-32bit branch: 8cd72983 rv1126: fix macro RG_MAP_SECURE Update feature: 8cd72983 rv1126: fix macro RG_MAP_
rv1126: tee with ta: update version to v1.18
Build from optee commit in develop-next-32bit branch: 8cd72983 rv1126: fix macro RG_MAP_SECURE Update feature: 8cd72983 rv1126: fix macro RG_MAP_SECURE ef89b5c2 rockchip: fix err of parsing ddr_parameter 2c6573a7 rockchip: rv1126: fix error of parenthesis matching in sgrf_init 1e75c939 plat-rockchip: fiq-debugger: adjust the usage of fiq_debugger.tgt_cpu 9f935616 pta: unnecessary to free share memory when close session 7fcbc47e plat-rockchip: fix CFG_RK_STATIC_MEM_PARAM define err d9140b1b rv1126: conf.mk: use atags to pass parameter
Change-Id: Ie2f05d7b5fb133a2b4c1035edd8632505c8dfcb2 Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
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| feb5aa08 | 08-Jun-2021 |
Joseph Chen <chenjh@rock-chips.com> |
rk3568: bl31 ultra: update version to v2.05
Build from ATF commit: 7bc959925 plat: rk3568: dmc: update version to V1.01 and add ddr_get_freq_info update feature: 7bc959925 plat: rk3568: dmc:
rk3568: bl31 ultra: update version to v2.05
Build from ATF commit: 7bc959925 plat: rk3568: dmc: update version to V1.01 and add ddr_get_freq_info update feature: 7bc959925 plat: rk3568: dmc: update version to V1.01 and add ddr_get_freq_info d2e0ef53d plat: rk3568: select the default suspend 32k clock from the PVTM f8297ce88 rockchip_exceptions: adjust the usage of uartdbg_uart_info.tgt_cpu d053a1087 rockchip: fiq debugger: don't disable fiq if fiq from el2 354236216 rockchip_exceptions: save/restore el2 register if fiq-debugger from el2 02bab0c8f BACKPORT: lib: el3_runtime: Fix SPE system registers in el2_sysregs_context 2c7c36d92 plat: rk3568: support cache ecc. cda1658bc plat: rk3568: config the pmugrf_reset_hold bit c2d509965 plat: rk3568: save and restore PMUCRU_PMUCLKSEL_CON00 9b05de3a1 plat: rk3568: dump the wakeup irq 270aa3847 plat: rk3568: dmc: rectiyf LPDDR4 MR14 value
Signed-off-by: Joseph Chen <chenjh@rock-chips.com> Change-Id: I3e00968594fae0ceed781dbc130157b6d114cf76
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| 7be392f7 | 02-Jun-2021 |
shengfei Xu <xsf@rock-chips.com> |
rk3568: bl31: update version to v1.25
Build from ATF commit: bd3bc346f plat: rk3568: select the default suspend 32k clock from the PVTM update feature: bd3bc346f plat: rk3568: select the default s
rk3568: bl31: update version to v1.25
Build from ATF commit: bd3bc346f plat: rk3568: select the default suspend 32k clock from the PVTM update feature: bd3bc346f plat: rk3568: select the default suspend 32k clock from the PVTM Signed-off-by: shengfei Xu <xsf@rock-chips.com> Change-Id: Ifcf9119cfd26d158a7f0b7c7e2a5d16a8849255f
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| 7d631e0d | 01-Jun-2021 |
shengfei Xu <xsf@rock-chips.com> |
rk3568: bl31: update version to v1.24
Build from ATF commit: cda1658bc plat: rk3568: config the pmugrf_reset_hold bit update feature: cda1658bc plat: rk3568: config the pmugrf_reset_hold bit
Sign
rk3568: bl31: update version to v1.24
Build from ATF commit: cda1658bc plat: rk3568: config the pmugrf_reset_hold bit update feature: cda1658bc plat: rk3568: config the pmugrf_reset_hold bit
Signed-off-by: shengfei Xu <xsf@rock-chips.com> Change-Id: Iff421e98ab2ab7ebfb6555f254ab6159fd65cb6c
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| 02bb26cd | 28-May-2021 |
Zhihuan He <huan.he@rock-chips.com> |
rv1108: ddr: update ddr version to V1.10 20210528
build from: 8b1eaeb Version: DDR Version V1.10 20210528 update feature: 49072a6 ddr: enable ssmod support
Signed-off-by: Zhihuan He <huan.he@rock
rv1108: ddr: update ddr version to V1.10 20210528
build from: 8b1eaeb Version: DDR Version V1.10 20210528 update feature: 49072a6 ddr: enable ssmod support
Signed-off-by: Zhihuan He <huan.he@rock-chips.com> Change-Id: Ic67e5ea5aa300e307a174d52f8a0ec41938b4bce
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| c3c03f68 | 28-May-2021 |
Zhihuan He <huan.he@rock-chips.com> |
rk322xh: bl31: update version to v1.46
Build from ATF commit: dfd73e4 commit_elf.sh: use make.sh to compile out the release version
update feature: 3479aa9 plat: rk322xh: remove ssmod and dsmpd w
rk322xh: bl31: update version to v1.46
Build from ATF commit: dfd73e4 commit_elf.sh: use make.sh to compile out the release version
update feature: 3479aa9 plat: rk322xh: remove ssmod and dsmpd when pll setting 5cb729f plat: rk322xh: init: config hdcp key
Signed-off-by: Zhihuan He <huan.he@rock-chips.com> Change-Id: If8b92c809debb7681a715e35cea76a978a404fe9
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| cb1fe674 | 28-May-2021 |
Zhihuan He <huan.he@rock-chips.com> |
rk1808: ddr: update to v1.05 20210113
build from: b9e7e0b79c dram init: rk1808: update ddr bin version to v1.05 update feature: 375b118e2d drivers: ram: rk1808: add ssmod support
Signed-off-by: Z
rk1808: ddr: update to v1.05 20210113
build from: b9e7e0b79c dram init: rk1808: update ddr bin version to v1.05 update feature: 375b118e2d drivers: ram: rk1808: add ssmod support
Signed-off-by: Zhihuan He <huan.he@rock-chips.com> Change-Id: Idb9bdedbf9e9fcaf3ed80a7d38738b407feaa36c
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| 6bd18410 | 15-Mar-2021 |
Zhihuan He <huan.he@rock-chips.com> |
rk3308: ddr: update version to v1.31
build from: 77f3f934ae rk356x: ddr: update ddr bin to v1.05
Update feature: ece7f0b94a rockchip: rk3308: dram_init: updata to version 1.31 e42e0449de drivers
rk3308: ddr: update version to v1.31
build from: 77f3f934ae rk356x: ddr: update ddr bin to v1.05
Update feature: ece7f0b94a rockchip: rk3308: dram_init: updata to version 1.31 e42e0449de drivers: ram: rk3308: delete unnecessary code deeaa9275a drivers: ram: rk3308: fix clksel get for reduce size c8878d51ba drivers: ram: rk3308: get ddr freq from loader param cfdb6e9b56 drivers: ram: rk3308: get ddr timing from ini file 169bf7c56f drivers: ram: rk3308: add ssmod support
Signed-off-by: Zhihuan He <huan.he@rock-chips.com> Change-Id: I0f8bef8dbfd138b53df440267d2cbfd8c48b3c2c
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| 11fd61f7 | 12-Jan-2021 |
Zhihuan He <huan.he@rock-chips.com> |
rk322xh/rk3328: ddr: update ddr init code to v1.17
print info: DDR Version 1.17 20210112 from commit: 5886a50 rk322xh: update DDR Version 1.17 20210528 update feature: 5886a50 rk322xh: update DDR
rk322xh/rk3328: ddr: update ddr init code to v1.17
print info: DDR Version 1.17 20210112 from commit: 5886a50 rk322xh: update DDR Version 1.17 20210528 update feature: 5886a50 rk322xh: update DDR Version 1.17 20210528 0b0e600 rk322xh: fix DDR3 MR0 tWR err in low freq c4d58c7 rk322xh: ddr: fix MR6 tccd_L err bb5c91f rk322xh: ddr: add support ssmod d2f0c46 rk322xH: ddr: add DPLL power down and up
Signed-off-by: Zhihuan He <huan.he@rock-chips.com> Change-Id: I382ee21ef5d9a1a93e2a7e7e81ee788daf5f59ff
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| 984b1f51 | 11-Jan-2021 |
Zhihuan He <huan.he@rock-chips.com> |
rk3326: ddr: update ddr bin to v1.16
build from: 2f76446 rk3326/px30: ddr: updata to v1.16 20210528
update feature: 69540a9 rk3326/px30: ddr: fix DDR4 MR6 tccd_L err 14551bb rk3326/px30: ddr: fi
rk3326: ddr: update ddr bin to v1.16
build from: 2f76446 rk3326/px30: ddr: updata to v1.16 20210528
update feature: 69540a9 rk3326/px30: ddr: fix DDR4 MR6 tccd_L err 14551bb rk3326/px30: ddr: fix MR0 tWR err in low freq 6f6714e rk3326/px30: ddr: limit max ddr.bin size to 10KB 1e8bea7 rk3326/px30: ddr: add support ssmod 8c20176 rk3326/px30: ddr: add DPLL power down and up
Signed-off-by: Zhihuan He <huan.he@rock-chips.com> Change-Id: Id6ed6c9fa52e460b95c05292ec9c9c50d74de188
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| 413d2f55 | 11-Jan-2021 |
Zhihuan He <huan.he@rock-chips.com> |
px30: ddr: update ddr bin to v1.16
build from: 2f76446 rk3326/px30: ddr: updata to v1.16 20210528
update feature: 69540a9 rk3326/px30: ddr: fix DDR4 MR6 tccd_L err 14551bb rk3326/px30: ddr: fix
px30: ddr: update ddr bin to v1.16
build from: 2f76446 rk3326/px30: ddr: updata to v1.16 20210528
update feature: 69540a9 rk3326/px30: ddr: fix DDR4 MR6 tccd_L err 14551bb rk3326/px30: ddr: fix MR0 tWR err in low freq 6f6714e rk3326/px30: ddr: limit max ddr.bin size to 10KB 1e8bea7 rk3326/px30: ddr: add support ssmod 8c20176 rk3326/px30: ddr: add DPLL power down and up
Signed-off-by: Zhihuan He <huan.he@rock-chips.com> Change-Id: Id1b3ff152a756cd18acb00a65482127063bcb541
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| 73945d35 | 19-May-2021 |
Tang Yun ping <typ@rock-chips.com> |
rk3566: ddr: update ddr bin to v1.08
build from: fdf3368d38 rk356x: ddr: update ddr bin to v1.08
build command: ./make.sh rk3568
update feature: 87531a7796 rk356x: ddr: fix otp operate b
rk3566: ddr: update ddr bin to v1.08
build from: fdf3368d38 rk356x: ddr: update ddr bin to v1.08
build command: ./make.sh rk3568
update feature: 87531a7796 rk356x: ddr: fix otp operate bug 9a4c526b6c rk356x: ddr: default lp4 active_ranks set to 0x3 9b565d229e rk356x: ddr: fix lpddr4/4x clk skew calculate bug 9b17bb3bce rk356x: ddr: update ddr4 1332/1560 timing
Signed-off-by: Tang Yun ping <typ@rock-chips.com> Change-Id: If71477d10a66b819b9e712eff58221b7800ea815
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| 443d8a34 | 19-May-2021 |
Tang Yun ping <typ@rock-chips.com> |
rk3568: ddr: update ddr bin to v1.08
build from: fdf3368d38 rk356x: ddr: update ddr bin to v1.08 build command: ./make.sh rk3568
update feature: 87531a7796 rk356x: ddr: fix otp operate bug 9a4c
rk3568: ddr: update ddr bin to v1.08
build from: fdf3368d38 rk356x: ddr: update ddr bin to v1.08 build command: ./make.sh rk3568
update feature: 87531a7796 rk356x: ddr: fix otp operate bug 9a4c526b6c rk356x: ddr: default lp4 active_ranks set to 0x3 9b565d229e rk356x: ddr: fix lpddr4/4x clk skew calculate bug 9b17bb3bce rk356x: ddr: update ddr4 1332/1560 timing
Signed-off-by: Tang Yun ping <typ@rock-chips.com> Change-Id: Ifc012b25229156b383162bf6f90e8fa2587c4589
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| 6e5a6beb | 26-May-2021 |
shengfei Xu <xsf@rock-chips.com> |
rk3568: bl31: update version to v1.23
Build from ATF commit: c2d509965 plat: rk3568: save and restore PMUCRU_PMUCLKSEL_CON00 update feature: c2d509965 plat: rk3568: save and restore PMUCRU_PMUCLKS
rk3568: bl31: update version to v1.23
Build from ATF commit: c2d509965 plat: rk3568: save and restore PMUCRU_PMUCLKSEL_CON00 update feature: c2d509965 plat: rk3568: save and restore PMUCRU_PMUCLKSEL_CON00 9b05de3a1 plat: rk3568: dump the wakeup irq 270aa3847 plat: rk3568: dmc: rectiyf LPDDR4 MR14 value 4214e1b9b plat: rk3568: correct osc 24M switch logic 6bac5da6d plat: rk3568: dmc: don't power down DDR4 VREF_OUT when suspend c75f366a6 plat: rk3568: disable GPIO debounce for system suspend 3c3da02d4 plat: rk3568: add comment for easy to backtrack the reason 3876f0dda plat: rk3568: add RK_ENABLE_JTAG configure
Signed-off-by: shengfei Xu <xsf@rock-chips.com> Change-Id: I59ffde2a0fd3fa16411a26d79a6327e5a841a53f
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| 649039a7 | 17-May-2021 |
Zhihuan He <huan.he@rock-chips.com> |
rk3399pro: ddr: update ddr version to v1.25 20210517
build from: ca6be15 Version: DDR Version 1.25 20210517 update feature: 0920221 rk3399: ddr: add efuse to limit freq to 666 0ee6cdc rk3399: ddr
rk3399pro: ddr: update ddr version to v1.25 20210517
build from: ca6be15 Version: DDR Version 1.25 20210517 update feature: 0920221 rk3399: ddr: add efuse to limit freq to 666 0ee6cdc rk3399: ddr: fix no uart init bug 917b12c rk3399: ddr: add support ssmod
Signed-off-by: Zhihuan He <huan.he@rock-chips.com> Change-Id: I1d5795912b086bd446fffce128e26482e36b5415
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| b46c088e | 17-May-2021 |
Zhihuan He <huan.he@rock-chips.com> |
rk3399: ddr: update ddr version to v1.25 20210517
build from: ca6be15 Version: DDR Version 1.25 20210517 update feature: 0920221 rk3399: ddr: add efuse to limit freq to 666 0ee6cdc rk3399: ddr: f
rk3399: ddr: update ddr version to v1.25 20210517
build from: ca6be15 Version: DDR Version 1.25 20210517 update feature: 0920221 rk3399: ddr: add efuse to limit freq to 666 0ee6cdc rk3399: ddr: fix no uart init bug 917b12c rk3399: ddr: add support ssmod
Signed-off-by: Zhihuan He <huan.he@rock-chips.com> Change-Id: Iaf607e85e557708247438ae4a967771d15fe09ab
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| 38cda7df | 21-Apr-2021 |
Yifeng Zhao <yifeng.zhao@rock-chips.com> |
rk3568: add ramboot support
from rk_boot_all: commit id: 379f85037
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> Change-Id: If80e525f0cfcc1cb05b4fca824965aee259ba7ed |
| 22b0d3f6 | 18-May-2021 |
Joseph Chen <chenjh@rock-chips.com> |
rk3568: bl31 ultra: update version to v2.04
Build from ATF commit: 270aa3847 plat: rk3568: dmc: rectiyf LPDDR4 MR14 value update feature: 270aa3847 plat: rk3568: dmc: rectiyf LPDDR4 MR14 val
rk3568: bl31 ultra: update version to v2.04
Build from ATF commit: 270aa3847 plat: rk3568: dmc: rectiyf LPDDR4 MR14 value update feature: 270aa3847 plat: rk3568: dmc: rectiyf LPDDR4 MR14 value 4214e1b9b plat: rk3568: correct osc 24M switch logic 6bac5da6d plat: rk3568: dmc: don't power down DDR4 VREF_OUT when suspend c75f366a6 plat: rk3568: disable GPIO debounce for system suspend 3c3da02d4 plat: rk3568: add comment for easy to backtrack the reason 3876f0dda plat: rk3568: add RK_ENABLE_JTAG configure 6b10c1bb5 plat: rk3568: put status info in ultra_info()
Signed-off-by: Joseph Chen <chenjh@rock-chips.com> Change-Id: Iff7291034744a0cd263b4c82531a7262921fae6e
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| 72328cf6 | 14-May-2021 |
Tang Yun ping <typ@rock-chips.com> |
rk3566: ddr: add print off ultra ddr bin
build from: 7326dc9e6f rk356x: ddr: update ultra ddr bin to v1.07 build command: ./make.sh rk3568
update feature: eb7cea41bb rk356x: ddr: fsp_param add s
rk3566: ddr: add print off ultra ddr bin
build from: 7326dc9e6f rk356x: ddr: update ultra ddr bin to v1.07 build command: ./make.sh rk3568
update feature: eb7cea41bb rk356x: ddr: fsp_param add save ca skew for DFS ab6ba1fc16 rk356x: ddr: resume: use LDO6 to decide run resume sequency or not 89c68153e2 rk356x: ddr: fix lpddr3 bug
Signed-off-by: Tang Yun ping <typ@rock-chips.com> Change-Id: I377ba34600171b6cadaf1d6609d3893dc51134c1
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| efeaf880 | 13-May-2021 |
Joseph Chen <chenjh@rock-chips.com> |
rk3568: bl31: remove unused file
Signed-off-by: Joseph Chen <chenjh@rock-chips.com> Change-Id: If6d20e991eead69f0c9a3f2b334e92d25fb7f31a
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| 9fdf14cc | 08-May-2021 |
Weixin Zhou <zwx@rock-chips.com> |
rk3568: bl31: update version to v1.22
Build from ATF commit: 6b10c1bb5 plat: rk3568: put status info in ultra_info() update feature: 6b10c1bb5 plat: rk3568: put status info in ultra_info() b83481
rk3568: bl31: update version to v1.22
Build from ATF commit: 6b10c1bb5 plat: rk3568: put status info in ultra_info() update feature: 6b10c1bb5 plat: rk3568: put status info in ultra_info() b834819eb plat: rk3568: disable pclk_stimer clk when VD_LOGIC keep on 34585499d plat: rk3568: disable gpio2B input_enable for reduce power dissipation 8104e1d0f plat: rk3568: keep osc 24M on lite sleep only f191f5d49 plat: rk3568: keep vd_logic on lite sleep only
Signed-off-by: Weixin Zhou <zwx@rock-chips.com> Change-Id: I7733f5e5b83e1f48b5010917ce7975fdf75e86a7
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| 2937f64c | 07-May-2021 |
Elon Zhang <zhangzj@rock-chips.com> |
rk3568: bl32: update version to v1.05
Build from optee commit in develop-next branch: 0b06ae94 rk3568: change TEE_LOAD_ADDR to 0x08400000
Update feature: 0b06ae94 rk3568: change TEE_LOAD_ADDR to
rk3568: bl32: update version to v1.05
Build from optee commit in develop-next branch: 0b06ae94 rk3568: change TEE_LOAD_ADDR to 0x08400000
Update feature: 0b06ae94 rk3568: change TEE_LOAD_ADDR to 0x08400000 1d4f7cfd rk3568: enlarge TA_RAM from 4M to 12M eeafddb5 otp: switch OTP R&W func to unified interface
Signed-off-by: Elon Zhang <zhangzj@rock-chips.com> Change-Id: Ib358ac85e8936f5d18bfdfb834ce8073823c92bb
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| 3681c3b8 | 08-May-2021 |
Joseph Chen <chenjh@rock-chips.com> |
rk3568: bl31 ultra: update version to v2.03
Build from: 6b10c1bb5 plat: rk3568: put status info in ultra_info()
Update features: 6b10c1bb5 plat: rk3568: put status info in ultra_info() b834819eb
rk3568: bl31 ultra: update version to v2.03
Build from: 6b10c1bb5 plat: rk3568: put status info in ultra_info()
Update features: 6b10c1bb5 plat: rk3568: put status info in ultra_info() b834819eb plat: rk3568: disable pclk_stimer clk when VD_LOGIC keep on 34585499d plat: rk3568: disable gpio2B input_enable for reduce power dissipation 8104e1d0f plat: rk3568: keep osc 24M on lite sleep only f191f5d49 plat: rk3568: keep vd_logic on lite sleep only ae0d3958f plat: rk3568: adjust npu pvtpll config b86e22653 plat: rk3568: dmc: set ddr clock in phase when suspend 4f2434ad5 plat: rk3568: save/restore the clock gate contol 5803d89e7 plat: rk3568: add core_dbgprcr_pwrdown_wfi() for common d17c40da3 plat: rk3568: dmc: setting clk_msch_div base on DPLL 405a815fd plat: rk3568: dmc: ignore CRU_DPLL_CON1.dsmpd when dfs a5f3cd0d1 plat: rk3568: add ddr ecc support 1e9739b4e plat: rk3568: fix typo
Signed-off-by: Joseph Chen <chenjh@rock-chips.com> Change-Id: I36c4f37e80520556eaf04dd105e971de8e1ab2d6
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