rk3399: bl31: update version to 1.16

compile with option "SPD=opteed"

Change-Id: I8a2be647caa14dc83d2a4b87b5f2c4480c789eba
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>

rk3399: bl31: update version to 1.15

Build from ATF commit:
d98d16e plat: rk3399: suspend: remove ddr debug log in suspend and dfs
update feature:
d98d16e plat: rk3399: suspend: remove ddr d

rk3399: bl31: update version to 1.15

Build from ATF commit:
d98d16e plat: rk3399: suspend: remove ddr debug log in suspend and dfs
update feature:
d98d16e plat: rk3399: suspend: remove ddr debug log in suspend and dfs
c4e7b9a plat: rk3399: suspend: support only one channel
824db84 rockchip: disable uart fiq when cpu/systerm resume

Change-Id: Ic2f4cd81bea778d1a107c5b1842f5b9f4140d5e2
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>

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px30: bl31: update version to v1.11

Build from ATF commit:
5f31f71 plat: px30: disable resetting output pin even reboot cmd.
update feature:
5f31f71 plat: px30: disable resetting output pin

px30: bl31: update version to v1.11

Build from ATF commit:
5f31f71 plat: px30: disable resetting output pin even reboot cmd.
update feature:
5f31f71 plat: px30: disable resetting output pin even reboot cmd.
43c09a4 plat: px30: dfs: add support lpddr2

Change-Id: Ia052605e109b284d5908b378737ec7c569d99e55
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>

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rk3326: bl31: update version to v1.11

Build from ATF commit:
5f31f71 plat: px30: disable resetting output pin even reboot cmd.
update feature:
5f31f71 plat: px30: disable resetting output pi

rk3326: bl31: update version to v1.11

Build from ATF commit:
5f31f71 plat: px30: disable resetting output pin even reboot cmd.
update feature:
5f31f71 plat: px30: disable resetting output pin even reboot cmd.
43c09a4 plat: px30: dfs: add support lpddr2

Change-Id: I223e629d5baf21998f95f96207d6e93c84288bd7
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>

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rk3399: ddr: update ddr init bin v1.11

built from ddr init project commit:
d6e7216 Version: DDR Version 1.11 20180509

update feature:
1.support 1 cs lpddr4
2.support lpddr4 only one channel
3.remo

rk3399: ddr: update ddr init bin v1.11

built from ddr init project commit:
d6e7216 Version: DDR Version 1.11 20180509

update feature:
1.support 1 cs lpddr4
2.support lpddr4 only one channel
3.remove some lpddr4 log

Change-Id: Iac48d346fb1e86193a82369d024100bd02dba6a5
Signed-off-by: CanYang He <hcy@rock-chips.com>

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px30: update ddr init bin to v1.07

print info: print info: DDR Version 1.07 20180323
from commit:
95d3ef5 rk3326: ddr: init code update to v1.07

Change-Id: I29c95aadd28cfcb598e5898669ea20c9aaed287

px30: update ddr init bin to v1.07

print info: print info: DDR Version 1.07 20180323
from commit:
95d3ef5 rk3326: ddr: init code update to v1.07

Change-Id: I29c95aadd28cfcb598e5898669ea20c9aaed2874
Signed-off-by: Tang Yun ping <typ@rock-chips.com>

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rk3326: update ddr init bin to v1.07

print info: print info: DDR Version 1.07 20180423
from commit:
95d3ef5 rk3326: ddr: init code update to v1.07

Change-Id: I7eb677af124cdc8121301ed468eeebb5a76f9

rk3326: update ddr init bin to v1.07

print info: print info: DDR Version 1.07 20180423
from commit:
95d3ef5 rk3326: ddr: init code update to v1.07

Change-Id: I7eb677af124cdc8121301ed468eeebb5a76f9a01
Signed-off-by: Tang Yun ping <typ@rock-chips.com>

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rk3308: ddr: update version to v1.19

from commit:
4a256e5ccf8d rk3308: DDR Version V1.19
change:
1.check boot memory device.If loader device turn to maskrom
device,download is normal.
2.adjust dq

rk3308: ddr: update version to v1.19

from commit:
4a256e5ccf8d rk3308: DDR Version V1.19
change:
1.check boot memory device.If loader device turn to maskrom
device,download is normal.
2.adjust dq10,dq11,dq14,dq15 de-skew for better dqs1 eye training.
3.reduce pll vco
4.change qos prority,reduce cpu QOS prority,improve
some QOS prority.
5.Do not clear grf_os_reg0 when boot mode is BOOT_BROM_DOWNLOAD

Change-Id: Ie7cb666c634ce41ea558acbd71096f0811fe3444
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>

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rk3308: bl31: update version to v1.03

Build from ATF commit:
4b75948 plat: px30: support soc_bus sip.
Update feature:
1. disable uart fiq when cpu/systerm resume;
2. enable non-secure world acces

rk3308: bl31: update version to v1.03

Build from ATF commit:
4b75948 plat: px30: support soc_bus sip.
Update feature:
1. disable uart fiq when cpu/systerm resume;
2. enable non-secure world access Peri QOS;

Change-Id: Id73a4356c0058e265679a0130b6b54580e7e0462
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

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px30: bl31: update version to v1.10

Build from ATF commit:
4b75948 plat: px30: support soc_bus sip.
update feature:
4b75948 plat: px30: support soc_bus sip.
824db84 rockchip: disable uar

px30: bl31: update version to v1.10

Build from ATF commit:
4b75948 plat: px30: support soc_bus sip.
update feature:
4b75948 plat: px30: support soc_bus sip.
824db84 rockchip: disable uart fiq when cpu/systerm resume
1d4b214 Revert "plat: px30: add cluster idle support

Change-Id: Ied43a2fd12ed35327f9220a37f9e18c388720da3
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>

show more ...

rk3326: bl31: update version to v1.10

Build from ATF commit:
4b75948 plat: px30: support soc_bus sip.
update feature:
4b75948 plat: px30: support soc_bus sip.
824db84 rockchip: disable u

rk3326: bl31: update version to v1.10

Build from ATF commit:
4b75948 plat: px30: support soc_bus sip.
update feature:
4b75948 plat: px30: support soc_bus sip.
824db84 rockchip: disable uart fiq when cpu/systerm resume
1d4b214 Revert "plat: px30: add cluster idle support

Change-Id: I1d96ec07071bd1808717e5ef13577a13abd554ff
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>

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rk322xh/rk3328: ddr: update ddr init code to v1.13

print info: DDR Version 1.13 20180428
from commit:
c25a53d rk322xh: ddr: update init code to v1.13

Change-Id: Iace65e548d00b9d50abf41aac9a29d2e5b

rk322xh/rk3328: ddr: update ddr init code to v1.13

print info: DDR Version 1.13 20180428
from commit:
c25a53d rk322xh: ddr: update init code to v1.13

Change-Id: Iace65e548d00b9d50abf41aac9a29d2e5bf7e1bb
Signed-off-by: Tang Yun ping <typ@rock-chips.com>

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rk3399: bl31: update version to 1.14

Build from ATF commit:
a11dd97 plat: rk3399: suspend: fix lpddr4 1 cs die resume fail
update feature:
1. a11dd97 plat: rk3399: suspend: fix lpddr4 1 cs d

rk3399: bl31: update version to 1.14

Build from ATF commit:
a11dd97 plat: rk3399: suspend: fix lpddr4 1 cs die resume fail
update feature:
1. a11dd97 plat: rk3399: suspend: fix lpddr4 1 cs die resume fail
2. bcbc322 plat: rk3399: suspend: fix lpddr4 after init frequency changed
3. 69d9b56 bl31: execute bl32_init() dynamically

Change-Id: I1783740344a7202978a2d8c699fcddbdc3eaefae
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>

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px30: bl31: update version to v1.09

Build from ATF commit:
4f8f7c9 plat: px30: suspend: save/restore i2c_con register
update feature:
4f8f7c9 plat: px30: suspend: save/restore i2c_con regist

px30: bl31: update version to v1.09

Build from ATF commit:
4f8f7c9 plat: px30: suspend: save/restore i2c_con register
update feature:
4f8f7c9 plat: px30: suspend: save/restore i2c_con register

Change-Id: I16fa2cd53780d5c0b80c79a02dcaab4d73983554
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>

show more ...

rk3326: bl31: update version to v1.09

Build from ATF commit:
4f8f7c9 plat: px30: suspend: save/restore i2c_con register
update feature:
4f8f7c9 plat: px30: suspend: save/restore i2c_con regi

rk3326: bl31: update version to v1.09

Build from ATF commit:
4f8f7c9 plat: px30: suspend: save/restore i2c_con register
update feature:
4f8f7c9 plat: px30: suspend: save/restore i2c_con register

Change-Id: Id3ee66c580af6d23de097323828ab93b9f1ec74c
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>

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rk3308: bl32: add initial version v1.00

Bl32 is default disabled for rk3308, build from:
b9d3a88 plat-rockchip: add rk3308 support

Change-Id: I7f983f5a4b7548f7456f9a9cb5604d6d68c14179
Signed-off-b

rk3308: bl32: add initial version v1.00

Bl32 is default disabled for rk3308, build from:
b9d3a88 plat-rockchip: add rk3308 support

Change-Id: I7f983f5a4b7548f7456f9a9cb5604d6d68c14179
Signed-off-by: Zhang Zhijie <zhangzj@rock-chips.com>

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rk3399: bl31: update version to 1.13

Build from ATF commit:
93a86df rockchip: Add RK3308 support
update feature:
1) 5ab1c72 rockchip: rockchip_sip_svc: add used SIP numbers definition
2)

rk3399: bl31: update version to 1.13

Build from ATF commit:
93a86df rockchip: Add RK3308 support
update feature:
1) 5ab1c72 rockchip: rockchip_sip_svc: add used SIP numbers definition
2) 92e94aa plat: rk3399: suspend: 400 to 800 with pd_center off pass version
3) 7bcd2a3 plat: rk3399: ddr: fix global reset fail when vdd_gpu power off
4) c81b210 plat: rk3399: ddr: fix ddrconfig shift error
5) a0e119f plat: rk3399: ddr: fix ddrconfig save error

Change-Id: If4c9a7434e0d9ef63e2a6f271b4ccc937771dc2d
Signed-off-by: shengfei Xu <xsf@rock-chips.com>

show more ...

px30: bl31: update version to v1.08

Build from ATF commit:
bf05006 plat: px30: suspend: fix judgement err of gic resume
update feature:
bf05006 plat: px30: suspend: fix judgement err of gic

px30: bl31: update version to v1.08

Build from ATF commit:
bf05006 plat: px30: suspend: fix judgement err of gic resume
update feature:
bf05006 plat: px30: suspend: fix judgement err of gic resume
bfeba24 plat: px30: use CPU for ddr scale frequency
25a0f1b plat: px30: add fiq func for stimer0.
ac2470d plat: px30: disable resetting output pin.
69d9b56 bl31: execute bl32_init() dynamically

Change-Id: Iaaf6de5ff84f688fc4e95fdeb38cdf1e70eabb4d
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>

show more ...

rk3326: bl31: update version to v1.08

Build from ATF commit:
bf05006 plat: px30: suspend: fix judgement err of gic resume
update feature:
bf05006 plat: px30: suspend: fix judgement err of gi

rk3326: bl31: update version to v1.08

Build from ATF commit:
bf05006 plat: px30: suspend: fix judgement err of gic resume
update feature:
bf05006 plat: px30: suspend: fix judgement err of gic resume
bfeba24 plat: px30: use CPU for ddr scale frequency
25a0f1b plat: px30: add fiq func for stimer0.
ac2470d plat: px30: disable resetting output pin.
69d9b56 bl31: execute bl32_init() dynamically

Change-Id: Icc3509a9f71f55a660e66198f4fe77a499a25d46
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>

show more ...

rk3326: update ddr init bin to v1.06

print info: print info: DDR Version 1.06 20180323
from commit:
32fd6bc rk3326: ddr: init code update to v1.06

Change-Id: I3b2ff1490e58090cc73997859879ac78f6

rk3326: update ddr init bin to v1.06

print info: print info: DDR Version 1.06 20180323
from commit:
32fd6bc rk3326: ddr: init code update to v1.06

Change-Id: I3b2ff1490e58090cc73997859879ac78f6d2e840
Signed-off-by: Tang Yun ping <typ@rock-chips.com>

show more ...

px30: update ddr init bin to v1.06

print info: print info: DDR Version 1.06 20180323
from commit:
32fd6bc rk3326: ddr: init code update to v1.06

Change-Id: Ied9760d8e1474217f58b3fc1fa4170bbce865fc

px30: update ddr init bin to v1.06

print info: print info: DDR Version 1.06 20180323
from commit:
32fd6bc rk3326: ddr: init code update to v1.06

Change-Id: Ied9760d8e1474217f58b3fc1fa4170bbce865fc8
Signed-off-by: Tang Yun ping <typ@rock-chips.com>

show more ...

rk3308: bl31: update version to v1.02

Build from ATF commit:
69d9b56 bl31: execute bl32_init() dynamically

Update features:
1. 69d9b56 bl31: execute bl32_init() dynamically
2. 35e0de4 p

rk3308: bl31: update version to v1.02

Build from ATF commit:
69d9b56 bl31: execute bl32_init() dynamically

Update features:
1. 69d9b56 bl31: execute bl32_init() dynamically
2. 35e0de4 plat: rk3308: dfs: add ddr_get_rate implement
3. e46f07e plat: rk3308: add optimise

Change-Id: I99ed333c38a8c1038120ab311602f3eeb2599995
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>

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rk3308: ddr: add initial version v1.11

from commit :
7b62dfc rk3308: DDR Version V1.11
add
1.set vpll0 in 1179.648MHz,vpll1 in 903.168MHz
2.ddr in vpll0,set 589MHz
3.adjusted deskew for a

rk3308: ddr: add initial version v1.11

from commit :
7b62dfc rk3308: DDR Version V1.11
add
1.set vpll0 in 1179.648MHz,vpll1 in 903.168MHz
2.ddr in vpll0,set 589MHz
3.adjusted deskew for aligning DQS and CK
4.delete clk 50% duty ratio setting in cru
5.set APLL,DPLL,VPLL0,VPLL1 without level shift
6.set pll vco high,but lower 3.2GHz,for minimum jitter.
7.add ddr scramble,include enable pmu pvtm.
8.updata ddr config grf_os_reg2,grf_os_reg3 to v1.08.

Change-Id: Ia459f53d7d9623f3af7e0de1edc2f99735d57c80
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>

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rk3308: bl31: add initial version v1.01

This is a temporary version, build from: c288f26

update features:
1. Support pwm regulator suspend voltage adjust;
2. Don't update voice VPLL.

Change-Id:

rk3308: bl31: add initial version v1.01

This is a temporary version, build from: c288f26

update features:
1. Support pwm regulator suspend voltage adjust;
2. Don't update voice VPLL.

Change-Id: I2620a245051a9cbd22ef81bdf9d19cf2ea5b4f28
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>

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rk3326: zftl: improve the processing mechanism of nand flash read and write

from loader commit 0d94125e9: zftl: improve the processing mechanism of nand flash read and write

Change-Id: I13c37f1a56f

rk3326: zftl: improve the processing mechanism of nand flash read and write

from loader commit 0d94125e9: zftl: improve the processing mechanism of nand flash read and write

Change-Id: I13c37f1a56f288f13bf17c5ed1992d363a0e6080
Signed-off-by: Yifeng Zhao <zyf@rock-chips.com>

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