| #
a0e7626f |
| 13-Nov-2015 |
Tang Yun ping <typ@rock-chips.com> |
rk3368: ddr init bin, bl30 update
1.RK3368_DDR_800M_V1.16: add detect dram die bandwidth. 2.bl30 V2.12: optimizing tRRD timing for DDR3, optimizing tRFC, tRCD, tRP, tRTW, tDQS for LPDDR3.
Change-Id
rk3368: ddr init bin, bl30 update
1.RK3368_DDR_800M_V1.16: add detect dram die bandwidth. 2.bl30 V2.12: optimizing tRRD timing for DDR3, optimizing tRFC, tRCD, tRP, tRTW, tDQS for LPDDR3.
Change-Id: I3fee74f6499dfbe7ba416c7f1bfe78fb17d02d5e Signed-off-by: Tang Yun ping <typ@rock-chips.com>
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| #
91037406 |
| 29-Oct-2015 |
cwz <cwz@rock-chips.com> |
rk3368: trust bl31 v1.7
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| #
5b969d13 |
| 28-Aug-2015 |
cwz <cwz@rock-chips.com> |
rk3368: Secureboot enable and check image when booting. 1. CONFIG_SECURE_RSA_KEY_IN_RAM config key get from ddr. 2. CONFIG_SECURE_RSA_KEY_ADDR config key address. 3. Secureboot change for
rk3368: Secureboot enable and check image when booting. 1. CONFIG_SECURE_RSA_KEY_IN_RAM config key get from ddr. 2. CONFIG_SECURE_RSA_KEY_ADDR config key address. 3. Secureboot change for support key in ddr. 4. bl31 v1.6 for crypto module error. 5. miniloader v2.40.
Signed-off-by: cwz <cwz@rock-chips.com>
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| #
834007ab |
| 23-Jul-2015 |
cwz <cwz@rock-chips.com> |
rk3368: trust v1.0, ddr/bl31/miniloader bin update.
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| #
ed121d3b |
| 11-Sep-2015 |
cwz <cwz@rock-chips.com> |
rk3368: trust bl30 v2.11.
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| #
13b7864d |
| 25-Aug-2015 |
cwz <cwz@rock-chips.com> |
rk3368: trust bl31 v1.5 and bl30 2.10.
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| #
03310673 |
| 13-Aug-2015 |
cwz <cwz@rock-chips.com> |
rk3368: trust bl31 v1.4.
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| #
ec0d9560 |
| 12-Aug-2015 |
cwz <cwz@rock-chips.com> |
rk3368: trust bl30 v2.09.
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| #
910f03ea |
| 05-Aug-2015 |
cwz <cwz@rock-chips.com> |
rk3368: trust bl30 v2.08.
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| #
059a9ca7 |
| 09-Jul-2015 |
cwz <cwz@rock-chips.com> |
rk3368: trust v0.9, bl30 v2.07.
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| #
f5a13f4b |
| 01-Jul-2015 |
cwz <cwz@rock-chips.com> |
rk3368: trust v0.8, bl30 v2.06.
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| #
4c74b59c |
| 26-Jun-2015 |
cwz <cwz@rock-chips.com> |
rk3368: trust v0.8, bl30 v2.05.
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| #
e96f1d5d |
| 16-Jun-2015 |
cwz <cwz@rock-chips.com> |
rk3368: trust v0.7 support merge bl32. 1. trust merge bl32 depend on CONFIG_RK_TRUSTOS; 2. trust_merger tool enable merge bl32; 3. Makefile enable --subfix depend on CONFIG_RK_TRUSTOS;
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| #
fa973ddf |
| 02-Jun-2015 |
cwz <cwz@rock-chips.com> |
rk tools: rk3368 miniloader v2.30, trust v0.6.
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| #
97bcee07 |
| 15-May-2015 |
cwz <cwz@rock-chips.com> |
rk3368: trust: bl31 version 1.2
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| #
4a960acc |
| 11-May-2015 |
cwz <cwz@rock-chips.com> |
rk3368: trust: bl31 v1.1, for kernel suspend/resume.
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| #
0e3c1959 |
| 11-May-2015 |
cwz <cwz@rock-chips.com> |
rk3368: trust image v0.4, bl30 v2.03: 1. mcu idle task move from sdram to ram; 2. adjust ddr3 dll bypass timing, fix 8cpus low freq handup.
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| #
35e4b59a |
| 04-May-2015 |
cwz <cwz@rock-chips.com> |
rk3368 trust: mcu bl30 bin version 2.02: 1. mcu sam memory map to internel ram - Start 4K. 2. bl30 main code running in ddr - Start 512K, Size 512K. 3. bl30 ddr freq change code running i
rk3368 trust: mcu bl30 bin version 2.02: 1. mcu sam memory map to internel ram - Start 4K. 2. bl30 main code running in ddr - Start 512K, Size 512K. 3. bl30 ddr freq change code running in ram - Start 4K, Size 8K. 4. PLS synchronous update kernel for ddr freq change function.
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| #
f778f1dc |
| 27-Apr-2015 |
cwz <cwz@rock-chips.com> |
rk_tools: trust.img version 0.2
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| #
95ce4a47 |
| 27-Apr-2015 |
cwz <cwz@rock-chips.com> |
rk_tools: trust config loader bl30 to 0xff8c1000
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| #
819a26b0 |
| 15-Apr-2015 |
cwz <cwz@rock-chips.com> |
rk_tools: rk3368 trust image bl31 bin v0.2.
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| #
dae73176 |
| 13-Apr-2015 |
cwz <cwz@rock-chips.com> |
rk_tools: Trust partition rename to trust.img.
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| #
3619e3e4 |
| 13-Apr-2015 |
cwz <cwz@rock-chips.com> |
rk_tools: TrustImage extension rename from bin to img.
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| #
affde547 |
| 10-Apr-2015 |
cwz <cwz@rock-chips.com> |
rk tools: fix RK3368TRUST.ini bl31 name error.
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| #
196d9472 |
| 09-Apr-2015 |
cwz <cwz@rock-chips.com> |
rk3368: mcu init enable depend on config CONFIG_RK_MCU when calling arch_early_init_r(). 1. TrustImage update bl30 bin v2.00; 2. mcu set clock div from gpll and cru dereset for running.
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