rk3326: bl32: update version to v2.19

Build from OPTEE commit in develop-next branch:
9f2aca7d1 pta: uboot_storedata_otp: reinit ssk when set security level2
Update features:
9f2aca7d1 pta:

rk3326: bl32: update version to v2.19

Build from OPTEE commit in develop-next branch:
9f2aca7d1 pta: uboot_storedata_otp: reinit ssk when set security level2
Update features:
9f2aca7d1 pta: uboot_storedata_otp: reinit ssk when set security level2
d038af9d2 pta: uboot_storedata_otp: add check for rpmb key
679d5bd8f core: tee: add func for check rpmb key is written
9be174551 rockchip: uart: Add real uart hw init
6b3714286 Revert "libcrypto: set RSA OAEP MGF1 MD function to SHA1"
6b9b39300 ta.mk: not copy lib/libcrypto/include to host_include
0ca603d39 plat-rockchip: modify conditions for read secure boot flag
fd6b94676 plat-rockchip: vendor_props: fix xtest regression_1006 fail

Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>
Change-Id: I69df3827275e4d90f7ec115eac11c87b06182043

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rk3326: bl32: update version to v2.18

Build from OPTEE commit in develop-next branch:
6c78a7d8c rk3506: Don't disable vccio4 IE by default
Update features:
6c78a7d8c rk3506: Don't disable vc

rk3326: bl32: update version to v2.18

Build from OPTEE commit in develop-next branch:
6c78a7d8c rk3506: Don't disable vccio4 IE by default
Update features:
6c78a7d8c rk3506: Don't disable vccio4 IE by default
d8ccdb1b5 pta: uboot_storedata_otp: add check for read toybrick ksn
4cd67e2b3 plat-rockchip: common: support soft ta encryption key
d19d25819 plat-rockchip: map MEM_AREA_RAM_NSEC to MEM_AREA_IO_NSEC
2aae11a16 rockchip: atags: add BOOT1P_PARAM related define
1bfd9b503 scripts: build_optee_os: Add FW_VERSION_PRINT

Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>
Change-Id: I3f02c029e2807f8378c6e66f5f2a3fec9fc75938

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rk3326: bl32: update version to v2.17

Build from OPTEE commit in develop-next branch:
7ab599eca
Update features:
7ab599eca
7bccc9d0b scripts: fixed build error when CFG_DEBUG=y
7eeac

rk3326: bl32: update version to v2.17

Build from OPTEE commit in develop-next branch:
7ab599eca
Update features:
7ab599eca
7bccc9d0b scripts: fixed build error when CFG_DEBUG=y
7eeac5fbf core: rpmb: change read data to multiple times
cb202f37a libutee: increase MPI_MEMPOOL_SIZE size
3210aa2eb plat-rockchip: implement itr_core_handler() not rely on CFG_FIQ
392302b07 UPSTREAM: core: tee_entry: fix array out of bounds check in cleanup_shm_refs()
185dc3c92 pta: crypto_service: optimization parameter check

Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
Change-Id: I81421a6d70772234f245b1bab8d9a678b95ad116

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rk3326: bl32: update version to v2.16

Build from OPTEE commit in develop-next branch:
185dc3c92 pta: crypto_service: optimization parameter check
Update features:
185dc3c92 pta: crypto_servi

rk3326: bl32: update version to v2.16

Build from OPTEE commit in develop-next branch:
185dc3c92 pta: crypto_service: optimization parameter check
Update features:
185dc3c92 pta: crypto_service: optimization parameter check
22c240efc pta: rockchip: rk_os_service: add parameter checking for trng
89b616c96 pta: uboot_storedata_otp: optimization parameter check
bde521b1e pta: uboot_storedata_efuse: optimization parameter check
8631500dc pta: uboot_storedata: optimization parameter check
819ac530d plat-rockchip: uart: set max timeout 5.6ms wait for uart busy
c2e6f9b66 drivers: hal_crypto: skip hash/tag valid check for V4
6d56b8ea5 pta: rockchip: enhanced parameter checking for R&W OTP
967d63292 pta: uboot_storedata_otp: optimize otp write function
7060bdbdb plat-rockchip: pstore: fix the error that rb->start is too big
ee7e1e84e core: ree_fs_open(): close dirfile on error
540ade275 core: arm: print tee memory usage
53b92eefa drivers: hal_crypto: modify print level for crypto version
a5847983c plat-rockchip: enable CFG_RK_OEM_ENCRYPT_DATA
a5be984aa pta: uboot_storedata_otp: support RW oem encrypt data
9b4140743 plat-rockchip: define OEM_ENCRYPT_DATA offset and size
c0f517747 drivers: hal_crypto: Fix the calculation error when the address exceeds 32bit
62aa10b78 kernel: link.mk: modify fwver print
322d721f4 rockchip: atags: Fix last valid tag be damaged when override tag
f41b05870 scripts: commit_bin.sh: support build with fwver
118a16b23 rockchip: support specify fwver during compilation
001a84604 rockchip: atags: add fwver tag support
d8a792882 core: arm: remove CFG_R1_NS_ENTRY_ADDR

Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>
Change-Id: Ie5264faa15e763c26b9ed2c090394e03d5fbb6b9

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rk3326: bl31: update version to v1.34

Build from ATF commit:
46064b2d5 plat: px30: dram: support 2x/4x refresh for
Extended temperature range

update feature:
46064b2d5 plat: px30: dram: support 2

rk3326: bl31: update version to v1.34

Build from ATF commit:
46064b2d5 plat: px30: dram: support 2x/4x refresh for
Extended temperature range

update feature:
46064b2d5 plat: px30: dram: support 2x/4x refresh for
Extended temperature range

Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
Change-Id: I6878e9c95e21649df071d6b6a379417dca078f96

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rk3326: bl32: update version to v2.15

Build from OPTEE commit in develop-next branch:
b5340fd65 rk3528: init hdcp key when bringup
Update features:
bcabf953b pta: crypto_service: modify para

rk3326: bl32: update version to v2.15

Build from OPTEE commit in develop-next branch:
b5340fd65 rk3528: init hdcp key when bringup
Update features:
bcabf953b pta: crypto_service: modify param check in oem otp key cipher
feccaa485 pta: uboot_storedata_otp: support check ta encryption key is written
9e41a3f1e pta: uboot_storedata: support set and get security flag
2e4ec1697 drivers: hal_crypto: fixed CRYPTO crash when using dynamic shared memory
64d17e36f pta: crypto_service: added the address parameter security check
74c6116b9 rk3326: enable user clk before user read
7b8c9847b pta: uboot_storedata_otp: enable kernel read secure boot flag
84db04157 pta: uboot_storedata_otp: enable kernel read vboot key hash
597e4214d core: main: register ddr to enable dynamic SHM
66a458730 core: lpae: increase PGT_CACHE_SIZE when define CFG_WITH_LPAE
ec7e85d54 plat-rockchip: support pstore for optee log

Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>
Change-Id: Ic13d006f3f82e2b8967dd35285a29d0a3b5a287c

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rk3326: bl31: update version to v1.33

Build from ATF commit:
0152b20d0 plat: px30: add amp support
update feature:
0152b20d0 plat: px30: add amp support
227fafce7 rockchip: gicv2: add fu

rk3326: bl31: update version to v1.33

Build from ATF commit:
0152b20d0 plat: px30: add amp support
update feature:
0152b20d0 plat: px30: add amp support
227fafce7 rockchip: gicv2: add functions for amp
098982bcc plat: px30: use common gicv2 save/restore function
1cd72fefa rockchip: fiq-debugger: support separate stack for os callback
05d32f7ef plat: rockchip: scmi: Add struct scmi_clock_t args to callbacks
4a8ea5e6d rockchip: add gicv2 save/restore function
946bbd849 plat: px30: sleep: support to use pll-deep-mode
74005d5d9 plat: px30: sleep: set pmu's count by actual pvtm's frequency

Change-Id: Ieb14a1d3646a3ed34c57009d59f0de9fb42031c9
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>

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rk3326: bl31: update version to v1.32

Build from ATF commit:
6f45bba91 plat: px30: do second reset if rbrom in px30s
update feature:
6f45bba91 plat: px30: do second reset if rbrom in px30s

rk3326: bl31: update version to v1.32

Build from ATF commit:
6f45bba91 plat: px30: do second reset if rbrom in px30s
update feature:
6f45bba91 plat: px30: do second reset if rbrom in px30s
99f86f801 plat: px30: disable reset out if reboot normal
8932810e4 plat: px30: resolve misjudgments about reboot_flag
ad0d2e72c plat: px30: compatible with the old loader
01ab909ae rockchip: support plat_bl31_inner.ld.S

Change-Id: I7a9711e7bbc20775ee9d0653ad0c5d054f6d1d11
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>

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rk3326: bl32: update version to v2.14

Build from OPTEE commit in develop-next branch:
d84087907 plat-rockchip: main: not call rk_uart_init if rk_atags disable serial
Update features:
d840879

rk3326: bl32: update version to v2.14

Build from OPTEE commit in develop-next branch:
d84087907 plat-rockchip: main: not call rk_uart_init if rk_atags disable serial
Update features:
d84087907 plat-rockchip: main: not call rk_uart_init if rk_atags disable serial
3e2bbe510 rk3326: set user dctrl before key reader init

Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>
Change-Id: I065f9842ad3cf836f04200ee05f825d3d39a6a8b

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rk3326: bl32: update version to v2.13

Build from OPTEE commit in develop-next branch:
3e2bbe510 rk3326: set user dctrl before key reader init
Update features:
3e2bbe510 rk3326: set user dctr

rk3326: bl32: update version to v2.13

Build from OPTEE commit in develop-next branch:
3e2bbe510 rk3326: set user dctrl before key reader init
Update features:
3e2bbe510 rk3326: set user dctrl before key reader init
87d94c5ef plat-rockchip: main: support hdcp key init via tee_entry_fast
0af3483b2 pta: crypto_service: support user ta call hard cipher
778974be4 core: tee: calculate node hash with meta default
4167319d3 core: tee: recreate dirf.db if open dirf.db fail

Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>
Change-Id: I75b662d9e8847a824b74b48a767a0674d2d13e03

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rk3326: bl31: update version to v1.31

Build from ATF commit:
244acd212 plat: px30-s: suspend: add ddr phy reg save

Update feature:
244acd212 plat: px30-s: suspend: add ddr phy reg save
680b18825

rk3326: bl31: update version to v1.31

Build from ATF commit:
244acd212 plat: px30-s: suspend: add ddr phy reg save

Update feature:
244acd212 plat: px30-s: suspend: add ddr phy reg save
680b18825 plat: px30-s: refactor ddr dfs set rate code
2d7dc684b plat: px30-s: add ddr eye scan func
f4b4c237c plat: px30-s: workaround x16 bw read training err
8abe5853e plat: px30-s: add default fsp config
2fa68b510 plat: px30-s: add de-skew info get from expanded param
faca0fa70 plat: px30-s: add get_wrlvl_val() fun after f1
6896d8e94 plat: px30-s: calculate tDQS2DQ before set rate

Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
Change-Id: Ib477c168e94f4a8534e3e71273e75024929962c6

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rk3326: bl31: update version to v1.30

Build from ATF commit:
5d208a630 plat: rockchip: scmi: not allowed rate = 0 to set rate
update feature:
61f4560ba plat: px30: sleep: save/restore cru_mo

rk3326: bl31: update version to v1.30

Build from ATF commit:
5d208a630 plat: rockchip: scmi: not allowed rate = 0 to set rate
update feature:
61f4560ba plat: px30: sleep: save/restore cru_mode if vdd_logic off

Change-Id: I38c02c37cde0b103f04b39b4833fac067d5eccbf
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>

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rk3326: bl31: update version to v1.29

Build from ATF commit:
7af4354ca plat: px30: sleep: disable timer before timer init
update feature:
7af4354ca plat: px30: sleep: disable timer before ti

rk3326: bl31: update version to v1.29

Build from ATF commit:
7af4354ca plat: px30: sleep: disable timer before timer init
update feature:
7af4354ca plat: px30: sleep: disable timer before timer init

Change-Id: I17a2089d575c364a7b92acc9e9309b92a05c148f
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>

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rk3326: bl31: update version to v1.28

Build from ATF commit:
edf5c3fbb plat: px30-s:workaround LP3 can not open cs1 odt in wr train

Update feature:
edf5c3fbb plat: px30-s:workaround LP3 can not o

rk3326: bl31: update version to v1.28

Build from ATF commit:
edf5c3fbb plat: px30-s:workaround LP3 can not open cs1 odt in wr train

Update feature:
edf5c3fbb plat: px30-s:workaround LP3 can not open cs1 odt in wr train
05922004b plat: px30-s: suspend: remove ddr_sr_fix_clk_phase() func
c088d3cc9 plat: px30-s: dram: remove phy dfi low power set
aa70ad066 plat: px30: don't init stimer1 if stimer1 is enabled
2877a2c9e plat: px30: support vdd_log off in suspend

Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
Change-Id: I6db79ea74891ee56c1f886eeb749c7b4ad308aad

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rk3326: bl32: update version to v2.12

Build from OPTEE commit in develop-next branch:
4167319d3 core: tee: recreate dirf.db if open dirf.db fail
Update features:
4167319d3 core: tee: recreat

rk3326: bl32: update version to v2.12

Build from OPTEE commit in develop-next branch:
4167319d3 core: tee: recreate dirf.db if open dirf.db fail
Update features:
4167319d3 core: tee: recreate dirf.db if open dirf.db fail
b61fa300d scripts: commit_bin: intercept the first 8 characters for LAST_CM
8e053a881 rockchip: remove duplicate definitions for toybrick seed
91c4147e7 pta: crypto_service: change some return code to be accurate
3167e3733 drivers: rockchip: hal_crypto: mask lockstep interrupt
3f0f0b052 pta: support check oem otp key is written
9af9076b0 rockchip: sys_ctrl: move sys ctrl code to common/ dir
48b7c13e2 pta: uboot_storedata_otp: modify parameter check
65daed964 pta: crypto_service: support oem otp key phys cipher
f5add58be core: TEE_GenerateKey support RSA key e = 3

Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>
Change-Id: I3f52db2bbfe52310a8798607f30da904ed96ebb7

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rk3326: bl31: update version to v1.27

Build from ATF commit:
96550638e plat: px30-s: dram: phy io ctrl save and resume
Update feature:
96550638e plat: px30-s: dram: phy io ctrl save and resume
16

rk3326: bl31: update version to v1.27

Build from ATF commit:
96550638e plat: px30-s: dram: phy io ctrl save and resume
Update feature:
96550638e plat: px30-s: dram: phy io ctrl save and resume
16b51a9f9 plat: px30-s: dram: fix ck/ckb to low before deepsleep
90c6c51f7 plat: rockchip: rk3588: Set gpll source clock div to 0
c5157a42e plat: px30-s: Restore DDR PHY dfi low power function
0de2c3db8 plat: px30: sleep: enter ddr sref by software
16fda9dd6 plat: px30s: suspend: add ddr resume support
91188bd6f plat: px30: suspend: support ddr resume

Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
Change-Id: I5cc4bf115cc194a6c6c21ea452031d0898fe1b97

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rk3326: bl31: update version to v1.26

Build from ATF commit:
12a2070163 plat: px30-s: dram: Disable LPDDR4 CA(except CK CS) ODT of CS1
Update feature:
12a2070163 plat: px30-s: dram: Disable LPDDR4

rk3326: bl31: update version to v1.26

Build from ATF commit:
12a2070163 plat: px30-s: dram: Disable LPDDR4 CA(except CK CS) ODT of CS1
Update feature:
12a2070163 plat: px30-s: dram: Disable LPDDR4 CA(except CK CS) ODT of CS1
f968b05b21 plat: px30-s: dram: Fix value of LPDDR3/LPDDR2 MR3 in cal_ds_odt()

Signed-off-by: Wesley Yao <wesley.yao@rock-chips.com>
Change-Id: Ic33a19750036de0b326bf717cf1e8603a4228e30

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rk3326: bl31: update version to v1.25

Build from ATF commit:
661655f41 plat: px30-s: Avoid DDR phy enter dfi low power
update feature:
661655f41 plat: px30-s: Avoid DDR phy e

rk3326: bl31: update version to v1.25

Build from ATF commit:
661655f41 plat: px30-s: Avoid DDR phy enter dfi low power
update feature:
661655f41 plat: px30-s: Avoid DDR phy enter dfi low power
35395b77a plat: px30-s: Get params of ssmod from dtsi to support dpll ssmod
898a221ec plat: px30s: Support LPDDR2
3f01db333 plat: px30-s: Prefetch DDR_STDBY_BASE and PMU_BASE before ddr freq change
bd02b56fd plat: px30s: ddr: fix tdqs2dq calculate err
942c5527a plat: px30s: ddr: set sr idle en/dis in ddr_set_auto_self_refresh()
6ff7126b5 plat: px30s: ddr: modify to timeout waiting dqs gate train done
0646dc72c plat: px30s: pmu: fix upctl save and recovery err
a1fd805fb plat: px30: pmu: disable ddr clk gate before suspend
d1670dca4 plat: px30s: ddr: modify dqs training default point
47fe4a754 plat: px30s: ddr: enable gate phy training logic clk
59ad9f9b0 plat: px30: sleep: use pmu_debug_sout function
898fdcd8a rockchip: only use plat_uart_base to initialize console
6e2576df1 plat: px30s: sleep: do pvtplls_suspend/pvtplls_resume

Change-Id: I46e198a4b474266210a651534d3e9ef8ceebb0de
Signed-off-by: Liang Chen <cl@rock-chips.com>

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rk3326: bl31: update version to v1.24

Build from ATF commit:
75d200365 plat: px30s: add support fsp init and dfs
update feature:
75d200365 plat: px30s: add support fsp init and dfs
c558d0311 plat

rk3326: bl31: update version to v1.24

Build from ATF commit:
75d200365 plat: px30s: add support fsp init and dfs
update feature:
75d200365 plat: px30s: add support fsp init and dfs
c558d0311 plat: px30: scmi: enable pvtpll clock for cpu/gpu
318d40339 plat: px30: support sram reuse section
c2e74efff rockchip: support sram_reuse section

Change-Id: If9d3cb2ffb2ad32af0c01f996a6ed42697552868
Signed-off-by: Liang Chen <cl@rock-chips.com>

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rk3326: bl32: update version to v2.11

Build from optee commit in develop-next branch:
f5add58b core: TEE_GenerateKey support RSA key e = 3

Update feature:
add299d6 rk3326: otp compatible wi

rk3326: bl32: update version to v2.11

Build from optee commit in develop-next branch:
f5add58b core: TEE_GenerateKey support RSA key e = 3

Update feature:
add299d6 rk3326: otp compatible with rk3326s
8f55d4bc rk3326: otp: separate external interface

Change-Id: I0b1c42410f674fa1333e4a8604feadc10993fe15
Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>

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rk3326: bl32: update version to v2.10

Build from optee commit in develop-next branch:
add299d6 rk3326: otp compatible with rk3326s

Update feature:
8f55d4bc rk3326: otp: separate external i

rk3326: bl32: update version to v2.10

Build from optee commit in develop-next branch:
add299d6 rk3326: otp compatible with rk3326s

Update feature:
8f55d4bc rk3326: otp: separate external interface

Change-Id: I431b6fee606b5332915d76e39928ee2d1bd8b1f0
Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>

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rk3326: bl32: update version to v2.01

Build from optee commit in develop-next branch:
50cc53fd pta: support R&W oem non-secure otp

Update feature:
5c3afe9d pta: rk_os_service: modify messag

rk3326: bl32: update version to v2.01

Build from optee commit in develop-next branch:
50cc53fd pta: support R&W oem non-secure otp

Update feature:
5c3afe9d pta: rk_os_service: modify message for illegal access
78d37d71 core: rpmb: compatible with old RPMB keys
7960156f rk3588: hamming weight support for security level

Change-Id: Id69b5f7d09b66e1ade3209d671b3ff1141f36ae2
Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>

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rk3326: bl32: update version to v2.00

Build from optee commit in develop-next branch:
7b4275734 rockchip: sip: add share mem page type define

Update feature:
1. Update OP-TEE version to V3.

rk3326: bl32: update version to v2.00

Build from optee commit in develop-next branch:
7b4275734 rockchip: sip: add share mem page type define

Update feature:
1. Update OP-TEE version to V3.13.0
2. Add build user info in boot up log

Change-Id: I5831f39fa93ede12197af65f680061a04b3a420f
Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>

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rk3326: bl31: update version to v1.23

Build from ATF commit:
fa02fd2 plat: px30: dram: support os_reg v2
update feature:
fa02fd2 plat: px30: dram: support os_reg v2
bc8b237 plat: px30: dram: add

rk3326: bl31: update version to v1.23

Build from ATF commit:
fa02fd2 plat: px30: dram: support os_reg v2
update feature:
fa02fd2 plat: px30: dram: support os_reg v2
bc8b237 plat: px30: dram: add dram dbg support
727877c plat: rockchip: common: dram: add dram dbg support
3804ade plat: px30: add monitor support

Signed-off-by: Zhihuan He <huan.he@rock-chips.com>
Change-Id: I9f6519c6cd9ca6258f3706499dc1bf7457db112c

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rk3326: bl31: update version to v1.22

Build from ATF commit:
3804ade4b
update feature:
d1cc80aa8 plat: rockchip: common: fix the min tWR overflow
6361591b0 plat: px30: remove dsmpd when

rk3326: bl31: update version to v1.22

Build from ATF commit:
3804ade4b
update feature:
d1cc80aa8 plat: rockchip: common: fix the min tWR overflow
6361591b0 plat: px30: remove dsmpd when pll setting

Change-Id: Ia5c2f2eac522bf00b7a15a232e2c9f223dc48507
Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>

show more ...