rk3368H/PX5: ddr: update ddr bin to v2.06

print info: DDR Version v2.06 20190903

build from:
389bcaf rk3368: ddr: update to v2.06
update feature:
fix Dram init bug of "unknow device".

Change-Id:

rk3368H/PX5: ddr: update ddr bin to v2.06

print info: DDR Version v2.06 20190903

build from:
389bcaf rk3368: ddr: update to v2.06
update feature:
fix Dram init bug of "unknow device".

Change-Id: I1ef50ae8af177d0d97f35015bdebcaa56a510b61
Signed-off-by: Tang Yun ping <typ@rock-chips.com>

show more ...

rk3308: miniloader: update loader to 1.17 version

from commit: 32687efbfe62f4a38c6871133338c92c8381c227

1.src: platform rk3308: add icache clean

Change-Id: If70d017e08eebfcd314864fbcabb8f45c7d8665

rk3308: miniloader: update loader to 1.17 version

from commit: 32687efbfe62f4a38c6871133338c92c8381c227

1.src: platform rk3308: add icache clean

Change-Id: If70d017e08eebfcd314864fbcabb8f45c7d86653
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

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rk3308: miniloader: update loader to 1.16 version

from commit: 72205102d1643973a7ec05064b2e31982bd6a9f9

1.add new SPI flash GD5F2GQ5UEYIG

Change-Id: Ic9d395db6e43c33815a2ce07faf96bd906644ecf
Signe

rk3308: miniloader: update loader to 1.16 version

from commit: 72205102d1643973a7ec05064b2e31982bd6a9f9

1.add new SPI flash GD5F2GQ5UEYIG

Change-Id: Ic9d395db6e43c33815a2ce07faf96bd906644ecf
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

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rk3288: loader: enable secure boot if loader sign.

from commit: 0dd6485 enable secure boot if loader sign.

Change-Id: Ib179260cde42bd1c5bb22404235315602509bba2
Signed-off-by: chenfen <chenfen@rock-

rk3288: loader: enable secure boot if loader sign.

from commit: 0dd6485 enable secure boot if loader sign.

Change-Id: Ib179260cde42bd1c5bb22404235315602509bba2
Signed-off-by: chenfen <chenfen@rock-chips.com>

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rk3308: support spi nand and slc nand without ftl

commit id: 9b6e0bcd: spi nand: support gpt without ftl

Change-Id: I620979d0d5a9f98973fb087ef2f26a1cd4d20601
Signed-off-by: Yifeng Zhao <zyf@rock-ch

rk3308: support spi nand and slc nand without ftl

commit id: 9b6e0bcd: spi nand: support gpt without ftl

Change-Id: I620979d0d5a9f98973fb087ef2f26a1cd4d20601
Signed-off-by: Yifeng Zhao <zyf@rock-chips.com>

show more ...

px30: loader_slc: update slc version to 1.19

Change-Id: Ifd8b3790a350d780bcd7b4537dd5d250336977ed
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>

px30: ddr: update ddr bin to v1.13

print info: DDR V1.13 20190814
build from:
d279ce2 rk3326/px30: ddr: updata to v1.13 20190814

update feature:
optimizing code size.

Change-Id: Iacc6e70b4

px30: ddr: update ddr bin to v1.13

print info: DDR V1.13 20190814
build from:
d279ce2 rk3326/px30: ddr: updata to v1.13 20190814

update feature:
optimizing code size.

Change-Id: Iacc6e70b4da5f6478fe9fee8d62717cc35b99fac
Signed-off-by: Tang Yun ping <typ@rock-chips.com>

show more ...

rk3326: ddr: update ddr bin to v1.13

print info: DDR V1.13 20190814
build from:
d279ce2 rk3326/px30: ddr: updata to v1.13 20190814

update feature:
optimizing code size.

Change-Id: I91da5b233e015

rk3326: ddr: update ddr bin to v1.13

print info: DDR V1.13 20190814
build from:
d279ce2 rk3326/px30: ddr: updata to v1.13 20190814

update feature:
optimizing code size.

Change-Id: I91da5b233e015dbea2648f02c7a650d70466760f
Signed-off-by: Tang Yun ping <typ@rock-chips.com>

show more ...

rk3326: loader: add A/B boot mode support.

from commit: ef487b56 add A/B boot mode support.

Change-Id: Id21ff54998c6cc006a32c055afc51d528788829f
Signed-off-by: Fen Chen <chenfen@rock-chips.com>

rk1808: loader: add public key atag.

from commit: 4a8a394 add public key atag.

Change-Id: Ie7906ee570586f0084c51dc07fd4bc202b2e8aa4
Signed-off-by: Fen Chen <chenfen@rock-chips.com>

rk3399pro: ddr: update ddr version to v1.23 20190709

build from:
f7529fe Version: DDR Version 1.23 20190709
update feature:
13a0b3f lpddr4: fix v1.22 block when advanced training done
cba7a71 lpd

rk3399pro: ddr: update ddr version to v1.23 20190709

build from:
f7529fe Version: DDR Version 1.23 20190709
update feature:
13a0b3f lpddr4: fix v1.22 block when advanced training done
cba7a71 lpddr4: fix read write-only register bit
7d1b640 lpddr4: fix dma sw training last delay pass bug
70c60fa lpddr4: fix tCKELCMD to max(7.5ns, 5nCK)

Change-Id: Ie5475d0411152a6cc70456e405ad6539fd4149bd
Signed-off-by: CanYang He <hcy@rock-chips.com>

show more ...

rk3368: ddr: update ddr init code to V2.05

print info: "DDR Version v2.05 20190701"

from commit:
37b9609 rk3368: ddr init code update to v2.05
update feature:
e07195a rk3368: ddr: add 2T mode con

rk3368: ddr: update ddr init code to V2.05

print info: "DDR Version v2.05 20190701"

from commit:
37b9609 rk3368: ddr init code update to v2.05
update feature:
e07195a rk3368: ddr: add 2T mode control by global parameter
8491b44 rk3368: enable 2T mode
597ce94 rk3368: ddr: fix wrong uart base address for atags

Change-Id: I7336b3d2b9f0901afdab37b1b2e10880e861fc02
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>

show more ...

rk322x: update ddr init bin to v1.09

print info: DDR Version V1.09 20190628

from commit:
805d41a rk322x: ddr update to v1.09

update feature:
e853ddd rk322x: ddr: add 2T mode control
396ea6e rk3

rk322x: update ddr init bin to v1.09

print info: DDR Version V1.09 20190628

from commit:
805d41a rk322x: ddr update to v1.09

update feature:
e853ddd rk322x: ddr: add 2T mode control
396ea6e rk322x: ddr: fix wrong uart base address for atags

Change-Id: Ic617d94368a82faa478d88d9965f2083bc0f792f
Signed-off-by: Zhihuan He <huan.he@rock-chips.com>

show more ...

rk3399: ddr: update ddr version to v1.23 20190709

build from:
f7529fe Version: DDR Version 1.23 20190709
update feature:
13a0b3f lpddr4: fix v1.22 block when advanced training done
cba7a71 lpddr4

rk3399: ddr: update ddr version to v1.23 20190709

build from:
f7529fe Version: DDR Version 1.23 20190709
update feature:
13a0b3f lpddr4: fix v1.22 block when advanced training done
cba7a71 lpddr4: fix read write-only register bit
7d1b640 lpddr4: fix dma sw training last delay pass bug
70c60fa lpddr4: fix tCKELCMD to max(7.5ns, 5nCK)

Change-Id: Ia3bfee77a7c53c759ab0fea5cf2daff378f40205
Signed-off-by: CanYang He <hcy@rock-chips.com>

show more ...

bin: rk3308: add usbplug and miniloader without FTL

uboot load address: 0x800 sectors.
trust load address: 0x1000 sectors.

Change-Id: I938b9248f006b0ce4abc69bc528719bdf998df8a
Signed-off-by: Yifeng

bin: rk3308: add usbplug and miniloader without FTL

uboot load address: 0x800 sectors.
trust load address: 0x1000 sectors.

Change-Id: I938b9248f006b0ce4abc69bc528719bdf998df8a
Signed-off-by: Yifeng Zhao <zyf@rock-chips.com>

show more ...

npu: lion: ddr: update to v1.03 20190524

build from:
cb0aa8f rockchip: rk1808: ddr: add ddr freq cofigurable
update feature:
1. enable 2T mode for DDR2/DDR3/DDR4
2. add unify ddr params(uart, ddr

npu: lion: ddr: update to v1.03 20190524

build from:
cb0aa8f rockchip: rk1808: ddr: add ddr freq cofigurable
update feature:
1. enable 2T mode for DDR2/DDR3/DDR4
2. add unify ddr params(uart, ddr freq..) configurable by
modify ddr bin.

Change-Id: I0953c9e2a1505428de917cf39d8463655ce2f455
Signed-off-by: Tang Yun ping <typ@rock-chips.com>

show more ...

rk1808: ddr: update to v1.03 20190524

build from:
cb0aa8f rockchip: rk1808: ddr: add ddr freq cofigurable
update feature:
1. enable 2T mode for DDR2/DDR3/DDR4
2. add unify ddr params(uart, ddr fr

rk1808: ddr: update to v1.03 20190524

build from:
cb0aa8f rockchip: rk1808: ddr: add ddr freq cofigurable
update feature:
1. enable 2T mode for DDR2/DDR3/DDR4
2. add unify ddr params(uart, ddr freq..) configurable by
modify ddr bin.

Change-Id: I2a321f1ec62dd3a69ed3e32a8837df5d47a6cfc4
Signed-off-by: Tang Yun ping <typ@rock-chips.com>

show more ...

rv110x: add rv110x_ddr3_v1.07.bin

SYR838 set core voltage from 1.0v to 1.15v

Change-Id: Ia8b4e4a9401ff2628e24a065befc77943c8c9d4f
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>

rk312x: loader: Add rk atags support.

from commit: 6da10d add rk atags bootdev.

Change-Id: Iec09b6d50fa6735f69ab9590fada97548721442e
Signed-off-by: Fen Chen <chenfen@rock-chips.com>

rk3036: loader: Add rk atags support.

from commit: 6da10d add rk atags bootdev.

Change-Id: I6c451d06c9508dbfdc229fda27d900162c36b43c
Signed-off-by: Fen Chen <chenfen@rock-chips.com>

rv110x: update ddr bin to v1.06

1. enable 2T command timing
To provide sufficient address setup time in heavily loaded memory
bus configuration.

Change-Id: Ia9cd664b0048816ce12b83c311e5b3044d66660b

rv110x: update ddr bin to v1.06

1. enable 2T command timing
To provide sufficient address setup time in heavily loaded memory
bus configuration.

Change-Id: Ia9cd664b0048816ce12b83c311e5b3044d66660b
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>

show more ...

rk3326: ARCH32: ddr: update ddr init bin to v1.12

print info: print info: DDR Version 1.12 20190528

from commit:
cbe7c08 rk3326: ddr: init code update to v1.12
update feature:
6e65fc3 rk332

rk3326: ARCH32: ddr: update ddr init bin to v1.12

print info: print info: DDR Version 1.12 20190528

from commit:
cbe7c08 rk3326: ddr: init code update to v1.12
update feature:
6e65fc3 rk3326: ddr: enable 2T mode for DDR3
4bd8b62 RK3326: ddr: fix wrong uart base address for atags

Change-Id: I7605ee08f29839873543e58644e9a9ecad515dc6
Signed-off-by: Tang Yun ping <typ@rock-chips.com>

show more ...

rk322xh/rk3328: ddr: update ddr init code to v1.16

print info: DDR Version 1.14 20190328
from commit:
aba5167 rk322xh: update DDR Version 1.16 20190528
update feature:
b4ea57c rk322xh: ddr: enable

rk322xh/rk3328: ddr: update ddr init code to v1.16

print info: DDR Version 1.14 20190328
from commit:
aba5167 rk322xh: update DDR Version 1.16 20190528
update feature:
b4ea57c rk322xh: ddr: enable 2T mode for DDR3
7134b25 rk322xH: ddr: fix wrong uart base address for atags

Change-Id: I5ecd6a0082c7c2afc3b1196d42dbad4a1adbe231
Signed-off-by: Tang Yun ping <typ@rock-chips.com>

show more ...

rk3326: ddr: update ddr init bin to v1.12

print info: print info: DDR Version 1.12 20190528

from commit:
cbe7c08 rk3326: ddr: init code update to v1.12
update feature:
6e65fc3 rk3326: ddr: enable

rk3326: ddr: update ddr init bin to v1.12

print info: print info: DDR Version 1.12 20190528

from commit:
cbe7c08 rk3326: ddr: init code update to v1.12
update feature:
6e65fc3 rk3326: ddr: enable 2T mode for DDR3
4bd8b62 RK3326: ddr: fix wrong uart base address for atags

Change-Id: I56b0d05320adaadc773ed585c816265c605604a8
Signed-off-by: Tang Yun ping <typ@rock-chips.com>

show more ...

px30: ddr: update ddr init bin to v1.12

print info: print info: DDR Version 1.12 20190528

from commit:
cbe7c08 rk3326: ddr: init code update to v1.12
update feature:
6e65fc3 rk3326: ddr: enable 2

px30: ddr: update ddr init bin to v1.12

print info: print info: DDR Version 1.12 20190528

from commit:
cbe7c08 rk3326: ddr: init code update to v1.12
update feature:
6e65fc3 rk3326: ddr: enable 2T mode for DDR3
4bd8b62 RK3326: ddr: fix wrong uart base address for atags

Change-Id: I8c0be9bd8e448732292957bf2900850173982aa0
Signed-off-by: Tang Yun ping <typ@rock-chips.com>

show more ...