| 7f4f78fb | 21-Jul-2021 |
zhijun.xie <xzj@rock-chips.com> |
rk3568: loader: add for spinand V1.09
from commit: b651e6 src: spinand: Support new devices
Add spinand miniloader.bin to support more plane-select spinand.
Change-Id: Ic2c71ed98b4c0510c70e1e81b54
rk3568: loader: add for spinand V1.09
from commit: b651e6 src: spinand: Support new devices
Add spinand miniloader.bin to support more plane-select spinand.
Change-Id: Ic2c71ed98b4c0510c70e1e81b54fc3cf758f9687 Signed-off-by: zhijun.xie <xzj@rock-chips.com> Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
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| 0c302903 | 28-Jun-2021 |
Zhihuan He <huan.he@rock-chips.com> |
rk3399pro: ddr: update ddr version to v1.26 20210628
build from: 930f42a Version: DDR Version 1.26 20210628
update feature: 83e2e29 rk3399: ddr: lp3/ddr3 limit freq to 666 for bin2 chip
Signed-o
rk3399pro: ddr: update ddr version to v1.26 20210628
build from: 930f42a Version: DDR Version 1.26 20210628
update feature: 83e2e29 rk3399: ddr: lp3/ddr3 limit freq to 666 for bin2 chip
Signed-off-by: Zhihuan He <huan.he@rock-chips.com> Change-Id: I7fdd46d052080d64a27f6c52f4c56c51a55040f8
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| a14a9fc5 | 28-Jun-2021 |
Zhihuan He <huan.he@rock-chips.com> |
rk3399: ddr: update ddr version to v1.26 20210628
build from: 930f42a Version: DDR Version 1.26 20210628
update feature: 83e2e29 rk3399: ddr: lp3/ddr3 limit freq to 666 for bin2 chip
Signed-off-
rk3399: ddr: update ddr version to v1.26 20210628
build from: 930f42a Version: DDR Version 1.26 20210628
update feature: 83e2e29 rk3399: ddr: lp3/ddr3 limit freq to 666 for bin2 chip
Signed-off-by: Zhihuan He <huan.he@rock-chips.com> Change-Id: I5a3e56eadf2e6134abf550979bd9abaf75bacee8
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| f3642b02 | 14-Jul-2021 |
Tang Yun ping <typ@rock-chips.com> |
rk3566: ddr: update ultra ddr bin to v1.08
build from: 6023a69949 rk356x: ddr: update ultra ddr bin to v1.08 build command: ./make.sh rk3568 update feature: 9296c56072 rk356x: ddr: add 3568s/m/j/
rk3566: ddr: update ultra ddr bin to v1.08
build from: 6023a69949 rk356x: ddr: update ultra ddr bin to v1.08 build command: ./make.sh rk3568 update feature: 9296c56072 rk356x: ddr: add 3568s/m/j/b2 support 7e8878d1d7 rk356x: ddr: fix reg_*_*_rxen_lp4 bug 10aade3a6a rk356x: ddr: allow user program otp in the user area aaccb8d8f1 rk356x: ddr: fix lpddr4/4x WDQS bug 46381ccb7c rk356x: ddr: fix dbw detect bug b043e57850 rk356x: ddr: fix otp operate bug 6b8cd55899 rk356x: ddr: default lp4 active_ranks set to 0x3 aa83a4734b rk356x: ddr: fix lpddr4/4x clk skew calculate bug d3dd95a7c6 rk356x: ddr: adjust lpddr4x vref and slew-rate 1de3994ced rk356x: ddr: fix lpddr4/4x ca training bug 9d70f844dd rk356x: ddr: fix some ddr bug 3a9d6e6bcd rk356x: ddr: fix otp read code bug 003c6eea54 rk356x: update rx dqs skew when init
Signed-off-by: Tang Yun ping <typ@rock-chips.com> Change-Id: Id81aab8bf21f131b730b0c6542f6eabedb7f5d0f
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| 07c7bfd2 | 02-Jun-2021 |
Zhihuan He <huan.he@rock-chips.com> |
rk322xh/rk3328: ddr: update ddr init code to v1.18
print info: DDR Version 1.18 20210602 from commit: 98b32cf rk322xh: update DDR Version 1.18 20210602 update feature: add limit ddr max freq to 53
rk322xh/rk3328: ddr: update ddr init code to v1.18
print info: DDR Version 1.18 20210602 from commit: 98b32cf rk322xh: update DDR Version 1.18 20210602 update feature: add limit ddr max freq to 533MHz for bin1 chip.
Signed-off-by: Zhihuan He <huan.he@rock-chips.com> Change-Id: Ia309ef21fbf406c9f487517960e03dd8e8dd30db
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| ac42a05f | 02-Jul-2021 |
Tang Yun ping <typ@rock-chips.com> |
rk3566: ddr: update ddr bin to v1.09
build from: d66fc41e9c rk356x: ddr: update ddr bin to v1.09 build command: ./make.sh rk3568
update feature: 74bdef59fd rk356x: ddr: add 3568s/m/j/b2 support
rk3566: ddr: update ddr bin to v1.09
build from: d66fc41e9c rk356x: ddr: update ddr bin to v1.09 build command: ./make.sh rk3568
update feature: 74bdef59fd rk356x: ddr: add 3568s/m/j/b2 support 3220a096ba rk356x: ddr: adjust print info 7dc3ec451a rk356x: ddr: fix reg_*_*_rxen_lp4 bug b16ddd2a97 rk356x: ddr: allow user program otp in the user area de4ccf565f rk356x: ddr: fix lpddr4/4x WDQS bug dd0befbb88 rk356x: ddr: disable cs1/cs3 ca odt f8c5ebd50e rk356x: ddr: add lpddr4 byte mode support 18225d611d rk356x: ddr: modify trfc base on real capacity 7e7f62e1e7 rk356x: ddr: auto detect 4 ch lpddr4/4x. db9aecc5ae rk356x: ddr: add more ddrconf support move to highest 256MB 5ee3419e72 rk356x: ddr: only support 4GB map to high 8GB-256MB
Signed-off-by: Tang Yun ping <typ@rock-chips.com> Change-Id: I0ecc0f69dd97598f45619d486fa732aab99544dc
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| 46e23dbf | 02-Jun-2021 |
Tang Yun ping <typ@rock-chips.com> |
rk3568: ddr: update ddr bin to v1.09
build from: d66fc41e9c rk356x: ddr: update ddr bin to v1.09 build command: ./make.sh rk3568
update feature: 74bdef59fd rk356x: ddr: add 3568s/m/j/b2 s
rk3568: ddr: update ddr bin to v1.09
build from: d66fc41e9c rk356x: ddr: update ddr bin to v1.09 build command: ./make.sh rk3568
update feature: 74bdef59fd rk356x: ddr: add 3568s/m/j/b2 support 3220a096ba rk356x: ddr: adjust print info 7dc3ec451a rk356x: ddr: fix reg_*_*_rxen_lp4 bug b16ddd2a97 rk356x: ddr: allow user program otp in the user area de4ccf565f rk356x: ddr: fix lpddr4/4x WDQS bug dd0befbb88 rk356x: ddr: disable cs1/cs3 ca odt f8c5ebd50e rk356x: ddr: add lpddr4 byte mode support 18225d611d rk356x: ddr: modify trfc base on real capacity 7e7f62e1e7 rk356x: ddr: auto detect 4 ch lpddr4/4x. db9aecc5ae rk356x: ddr: add more ddrconf support move to highest 256MB 5ee3419e72 rk356x: ddr: only support 4GB map to high 8GB-256MB
Signed-off-by: Tang Yun ping <typ@rock-chips.com> Change-Id: Ifc726aaf94150b9ce2841eb71ff388c7642a5e50
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| 1613d24d | 30-Jun-2021 |
Ziyuan Xu <xzy.xu@rock-chips.com> |
rv1126: tpl: update thunder boot ddr bin to v1.06
build from next-dev: b1b9d7fba4 drivers: ram: common: fix ssmod define err update feature: b1b9d7fba4 drivers: ram: common: fix ssmo
rv1126: tpl: update thunder boot ddr bin to v1.06
build from next-dev: b1b9d7fba4 drivers: ram: common: fix ssmod define err update feature: b1b9d7fba4 drivers: ram: common: fix ssmod define err d49e7c3403 drivers: ram: rv1126: fix the judgment of "set ctl address map fail" 06a17b4adf drivers: ram: rv1126: Turn on DQS_c 2k pull-up resistor to workaround WDQS control of LPDDR4/LPDDR4X 246ad23dbf drivers: ram: rk356x: fix read_mr() of LPDDR3 e90784abb2 rv1126: ddr: fix tx dqs bypass phase setting err c2a03d5d81 drivers: ram: rv1126: add support lpddr4x bf922fc800 drivers: ram: rv1126: fix calculating of MSCH_DeviceSize e2dc1cc022 drivers: ram: rv1126: Modify tRFC and related timing based on DDR capacity 330cd12fc3 drivers: ram: rv1126: fix return value of read_mr() 3993b0c711 drivers: ram: rv1126: Set default value of die bus with to x16 when bus width is x16/x32 of DDR3 9050e1f82e drivers: ram: rv1126: fix tZQLAT of LPDDR4 build command: CONFIG_SPL_KERNEL_BOOT=y for lpddr3 bin, CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE need set to 6. for lpddr4 bin, CONFIG_ROCKCHIP_TPL_INIT_DRAM_TYPE need set to 7. default CONFIG_ROCKCHIP_DRAM_EXTENDED_TEMP_SUPPORT=n, if you need extended temperature bin, you need enable "CONFIG_ROCKCHIP_DRAM\ _EXTENDED_TEMP_SUPPORT", then rebuild uboot. ./make.sh rv1126 && ./make.sh tpl. Note: the pre-build 528MHz binary disable ODT.
Change-Id: Ibb384f60d714535822202330d2c3ae3cef75337c Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
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| 11f4bc3f | 30-Jun-2021 |
Zhihuan He <huan.he@rock-chips.com> |
rv1126: ddr: update ddr bin to v1.06
build from u-boot-ddr: 78270c3ffa dram_init: rv1126: update to v1.06
update feature: d49e7c3403 drivers: ram: rv1126: fix the judgment of "set ctl address map
rv1126: ddr: update ddr bin to v1.06
build from u-boot-ddr: 78270c3ffa dram_init: rv1126: update to v1.06
update feature: d49e7c3403 drivers: ram: rv1126: fix the judgment of "set ctl address map fail" 06a17b4adf drivers: ram: rv1126: Turn on DQS_c 2k pull-up resistor to workaround WDQS control of LPDDR4/LPDDR4X 246ad23dbf drivers: ram: rk356x: fix read_mr() of LPDDR3 e90784abb2 rv1126: ddr: fix tx dqs bypass phase setting err c2a03d5d81 drivers: ram: rv1126: add support lpddr4x bf922fc800 drivers: ram: rv1126: fix calculating of MSCH_DeviceSize e2dc1cc022 drivers: ram: rv1126: Modify tRFC and related timing based on DDR capacity 330cd12fc3 drivers: ram: rv1126: fix return value of read_mr() 3993b0c711 drivers: ram: rv1126: Set default value of die bus with to x16 when bus width is x16/x32 of DDR3 9050e1f82e drivers: ram: rv1126: fix tZQLAT of LPDDR4
Signed-off-by: Zhihuan He <huan.he@rock-chips.com> Change-Id: I053cb27d5addb4bb85dd88a7780049b95b991029
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| 08144686 | 18-Jun-2021 |
Jon Lin <jon.lin@rock-chips.com> |
rk356x: loader: update version to v1.10
from commit: 98d5681 src: slc_flash: Support S34ML08G2
Change-Id: Ib95aa44b04c1a8ce1927a9bab10b04dbfb734a22 Signed-off-by: Jon Lin <jon.lin@rock-chips.com> |
| 3fce1f75 | 22-Jun-2021 |
Yifeng Zhao <yifeng.zhao@rock-chips.com> |
rk3568/rk3566: spl: nand: update version to v1.07
build from uboot commit: 7f48d41aa configs: rk3566 add rk3566-nand.config for nand
build command: ./make.sh rk3568
Signed-off-by: Yifen
rk3568/rk3566: spl: nand: update version to v1.07
build from uboot commit: 7f48d41aa configs: rk3566 add rk3566-nand.config for nand
build command: ./make.sh rk3568
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> Change-Id: I016823575aa7a6ec6c79758654281ab36e692595
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| cd37a230 | 11-Jun-2021 |
wlq <wlq@rock-chips.com> |
RKBOOT: rk3566: add RK3566MINIALL_NAND.ini for nand
Signed-off-by: wlq <wlq@rock-chips.com> Change-Id: If0a090c6a0fe5bd2c2ab82b6b152a141ca0119fc |
| 07ada3e8 | 01-Jun-2021 |
Jon Lin <jon.lin@rock-chips.com> |
rk356x: loader: update version to v1.09
from commit: b651e66 src: spinand: Support new devices
Change-Id: I089c9ad80fa357612fa42fd7e23f50fd818c997f Signed-off-by: Jon Lin <jon.lin@rock-chips.com> |
| 02bb26cd | 28-May-2021 |
Zhihuan He <huan.he@rock-chips.com> |
rv1108: ddr: update ddr version to V1.10 20210528
build from: 8b1eaeb Version: DDR Version V1.10 20210528 update feature: 49072a6 ddr: enable ssmod support
Signed-off-by: Zhihuan He <huan.he@rock
rv1108: ddr: update ddr version to V1.10 20210528
build from: 8b1eaeb Version: DDR Version V1.10 20210528 update feature: 49072a6 ddr: enable ssmod support
Signed-off-by: Zhihuan He <huan.he@rock-chips.com> Change-Id: Ic67e5ea5aa300e307a174d52f8a0ec41938b4bce
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| cb1fe674 | 28-May-2021 |
Zhihuan He <huan.he@rock-chips.com> |
rk1808: ddr: update to v1.05 20210113
build from: b9e7e0b79c dram init: rk1808: update ddr bin version to v1.05 update feature: 375b118e2d drivers: ram: rk1808: add ssmod support
Signed-off-by: Z
rk1808: ddr: update to v1.05 20210113
build from: b9e7e0b79c dram init: rk1808: update ddr bin version to v1.05 update feature: 375b118e2d drivers: ram: rk1808: add ssmod support
Signed-off-by: Zhihuan He <huan.he@rock-chips.com> Change-Id: Idb9bdedbf9e9fcaf3ed80a7d38738b407feaa36c
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| 6bd18410 | 15-Mar-2021 |
Zhihuan He <huan.he@rock-chips.com> |
rk3308: ddr: update version to v1.31
build from: 77f3f934ae rk356x: ddr: update ddr bin to v1.05
Update feature: ece7f0b94a rockchip: rk3308: dram_init: updata to version 1.31 e42e0449de drivers
rk3308: ddr: update version to v1.31
build from: 77f3f934ae rk356x: ddr: update ddr bin to v1.05
Update feature: ece7f0b94a rockchip: rk3308: dram_init: updata to version 1.31 e42e0449de drivers: ram: rk3308: delete unnecessary code deeaa9275a drivers: ram: rk3308: fix clksel get for reduce size c8878d51ba drivers: ram: rk3308: get ddr freq from loader param cfdb6e9b56 drivers: ram: rk3308: get ddr timing from ini file 169bf7c56f drivers: ram: rk3308: add ssmod support
Signed-off-by: Zhihuan He <huan.he@rock-chips.com> Change-Id: I0f8bef8dbfd138b53df440267d2cbfd8c48b3c2c
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| 11fd61f7 | 12-Jan-2021 |
Zhihuan He <huan.he@rock-chips.com> |
rk322xh/rk3328: ddr: update ddr init code to v1.17
print info: DDR Version 1.17 20210112 from commit: 5886a50 rk322xh: update DDR Version 1.17 20210528 update feature: 5886a50 rk322xh: update DDR
rk322xh/rk3328: ddr: update ddr init code to v1.17
print info: DDR Version 1.17 20210112 from commit: 5886a50 rk322xh: update DDR Version 1.17 20210528 update feature: 5886a50 rk322xh: update DDR Version 1.17 20210528 0b0e600 rk322xh: fix DDR3 MR0 tWR err in low freq c4d58c7 rk322xh: ddr: fix MR6 tccd_L err bb5c91f rk322xh: ddr: add support ssmod d2f0c46 rk322xH: ddr: add DPLL power down and up
Signed-off-by: Zhihuan He <huan.he@rock-chips.com> Change-Id: I382ee21ef5d9a1a93e2a7e7e81ee788daf5f59ff
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| 984b1f51 | 11-Jan-2021 |
Zhihuan He <huan.he@rock-chips.com> |
rk3326: ddr: update ddr bin to v1.16
build from: 2f76446 rk3326/px30: ddr: updata to v1.16 20210528
update feature: 69540a9 rk3326/px30: ddr: fix DDR4 MR6 tccd_L err 14551bb rk3326/px30: ddr: fi
rk3326: ddr: update ddr bin to v1.16
build from: 2f76446 rk3326/px30: ddr: updata to v1.16 20210528
update feature: 69540a9 rk3326/px30: ddr: fix DDR4 MR6 tccd_L err 14551bb rk3326/px30: ddr: fix MR0 tWR err in low freq 6f6714e rk3326/px30: ddr: limit max ddr.bin size to 10KB 1e8bea7 rk3326/px30: ddr: add support ssmod 8c20176 rk3326/px30: ddr: add DPLL power down and up
Signed-off-by: Zhihuan He <huan.he@rock-chips.com> Change-Id: Id6ed6c9fa52e460b95c05292ec9c9c50d74de188
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| 413d2f55 | 11-Jan-2021 |
Zhihuan He <huan.he@rock-chips.com> |
px30: ddr: update ddr bin to v1.16
build from: 2f76446 rk3326/px30: ddr: updata to v1.16 20210528
update feature: 69540a9 rk3326/px30: ddr: fix DDR4 MR6 tccd_L err 14551bb rk3326/px30: ddr: fix
px30: ddr: update ddr bin to v1.16
build from: 2f76446 rk3326/px30: ddr: updata to v1.16 20210528
update feature: 69540a9 rk3326/px30: ddr: fix DDR4 MR6 tccd_L err 14551bb rk3326/px30: ddr: fix MR0 tWR err in low freq 6f6714e rk3326/px30: ddr: limit max ddr.bin size to 10KB 1e8bea7 rk3326/px30: ddr: add support ssmod 8c20176 rk3326/px30: ddr: add DPLL power down and up
Signed-off-by: Zhihuan He <huan.he@rock-chips.com> Change-Id: Id1b3ff152a756cd18acb00a65482127063bcb541
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| 73945d35 | 19-May-2021 |
Tang Yun ping <typ@rock-chips.com> |
rk3566: ddr: update ddr bin to v1.08
build from: fdf3368d38 rk356x: ddr: update ddr bin to v1.08
build command: ./make.sh rk3568
update feature: 87531a7796 rk356x: ddr: fix otp operate b
rk3566: ddr: update ddr bin to v1.08
build from: fdf3368d38 rk356x: ddr: update ddr bin to v1.08
build command: ./make.sh rk3568
update feature: 87531a7796 rk356x: ddr: fix otp operate bug 9a4c526b6c rk356x: ddr: default lp4 active_ranks set to 0x3 9b565d229e rk356x: ddr: fix lpddr4/4x clk skew calculate bug 9b17bb3bce rk356x: ddr: update ddr4 1332/1560 timing
Signed-off-by: Tang Yun ping <typ@rock-chips.com> Change-Id: If71477d10a66b819b9e712eff58221b7800ea815
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| 443d8a34 | 19-May-2021 |
Tang Yun ping <typ@rock-chips.com> |
rk3568: ddr: update ddr bin to v1.08
build from: fdf3368d38 rk356x: ddr: update ddr bin to v1.08 build command: ./make.sh rk3568
update feature: 87531a7796 rk356x: ddr: fix otp operate bug 9a4c
rk3568: ddr: update ddr bin to v1.08
build from: fdf3368d38 rk356x: ddr: update ddr bin to v1.08 build command: ./make.sh rk3568
update feature: 87531a7796 rk356x: ddr: fix otp operate bug 9a4c526b6c rk356x: ddr: default lp4 active_ranks set to 0x3 9b565d229e rk356x: ddr: fix lpddr4/4x clk skew calculate bug 9b17bb3bce rk356x: ddr: update ddr4 1332/1560 timing
Signed-off-by: Tang Yun ping <typ@rock-chips.com> Change-Id: Ifc012b25229156b383162bf6f90e8fa2587c4589
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| d1c3f8e3 | 27-May-2021 |
Joseph Chen <chenjh@rock-chips.com> |
rk3568: ramboot: fix pack loader error
pack Input: ./RKBOOT/RK3568MINIALL_RAMBOOT.ini Traceback (most recent call last): File "boot_merger.py", line 1062, in <module> File "boot_merger.py", line
rk3568: ramboot: fix pack loader error
pack Input: ./RKBOOT/RK3568MINIALL_RAMBOOT.ini Traceback (most recent call last): File "boot_merger.py", line 1062, in <module> File "boot_merger.py", line 515, in boot_merger_main File "boot_merger.py", line 281, in create_new_idblock File "genericpath.py", line 50, in getsize FileNotFoundError: [Errno 2] No such file or directory: 'bin/rk35/rk3568_ddr_1560MHz_v1.06.bin' [12559] Failed to execute script boot_merger
Signed-off-by: Joseph Chen <chenjh@rock-chips.com> Change-Id: I626ed1af2199bb5cab13f6d8ad2ebe7b8bc8ce9b
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| 649039a7 | 17-May-2021 |
Zhihuan He <huan.he@rock-chips.com> |
rk3399pro: ddr: update ddr version to v1.25 20210517
build from: ca6be15 Version: DDR Version 1.25 20210517 update feature: 0920221 rk3399: ddr: add efuse to limit freq to 666 0ee6cdc rk3399: ddr
rk3399pro: ddr: update ddr version to v1.25 20210517
build from: ca6be15 Version: DDR Version 1.25 20210517 update feature: 0920221 rk3399: ddr: add efuse to limit freq to 666 0ee6cdc rk3399: ddr: fix no uart init bug 917b12c rk3399: ddr: add support ssmod
Signed-off-by: Zhihuan He <huan.he@rock-chips.com> Change-Id: I1d5795912b086bd446fffce128e26482e36b5415
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| b46c088e | 17-May-2021 |
Zhihuan He <huan.he@rock-chips.com> |
rk3399: ddr: update ddr version to v1.25 20210517
build from: ca6be15 Version: DDR Version 1.25 20210517 update feature: 0920221 rk3399: ddr: add efuse to limit freq to 666 0ee6cdc rk3399: ddr: f
rk3399: ddr: update ddr version to v1.25 20210517
build from: ca6be15 Version: DDR Version 1.25 20210517 update feature: 0920221 rk3399: ddr: add efuse to limit freq to 666 0ee6cdc rk3399: ddr: fix no uart init bug 917b12c rk3399: ddr: add support ssmod
Signed-off-by: Zhihuan He <huan.he@rock-chips.com> Change-Id: Iaf607e85e557708247438ae4a967771d15fe09ab
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| 38cda7df | 21-Apr-2021 |
Yifeng Zhao <yifeng.zhao@rock-chips.com> |
rk3568: add ramboot support
from rk_boot_all: commit id: 379f85037
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com> Change-Id: If80e525f0cfcc1cb05b4fca824965aee259ba7ed |