History log of /rk3399_rockchip-uboot/include/fsl_ddr_sdram.h (Results 26 – 46 of 46)
Revision Date Author Comments
# 7288c2c2 21-Mar-2015 York Sun <yorksun@freescale.com>

armv8/ls2085aqds: Add support of LS2085AQDS platform

The LS2085AQDS is an evaluatoin platform that supports the LS2085A
family SoCs. This patch add basic support of the platform.

Signed-off-by: Yor

armv8/ls2085aqds: Add support of LS2085AQDS platform

The LS2085AQDS is an evaluatoin platform that supports the LS2085A
family SoCs. This patch add basic support of the platform.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>

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# 9f9f0093 19-Mar-2015 York Sun <yorksun@freescale.com>

driver/ddr/fsl: Add workaround for DDR erratum A008511

This erratum only applies to general purpose DDR controllers in LS2.
It shouldn't be applied to DP-DDR controller. Check DDRC versoin number
be

driver/ddr/fsl: Add workaround for DDR erratum A008511

This erratum only applies to general purpose DDR controllers in LS2.
It shouldn't be applied to DP-DDR controller. Check DDRC versoin number
before applying workaround.

Signed-off-by: York Sun <yorksun@freescale.com>

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# 2c49323d 11-Dec-2014 Tom Rini <trini@ti.com>

Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq


# a7787b78 21-Nov-2014 Tang Yuantian <Yuantian.Tang@freescale.com>

fsl/sleep: updated the deep sleep framework for QorIQ platforms

With the introducing of generic board and ARM-based cores, current
deep sleep framework doesn't work anymore.
This patch will convert

fsl/sleep: updated the deep sleep framework for QorIQ platforms

With the introducing of generic board and ARM-based cores, current
deep sleep framework doesn't work anymore.
This patch will convert the current framework to adapt this change.
Basically it does:
1. Converts all the Freescale's DDR driver to support deep sleep.
2. Added basic framework support for ARM-based and PPC-based
cores separately.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

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# 3cc83f9d 07-Oct-2014 Minkyu Kang <mk7.kang@samsung.com>

Merge branch 'uboot'


# 2c2277f1 26-Sep-2014 Tom Rini <trini@ti.com>

Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq


# bb578322 21-Aug-2014 York Sun <yorksun@freescale.com>

driver/ddr/fsl: Fix tXP and tCKE

The driver was written using old DDR3 spec which only covers low speeds.
The value would be suboptimal for higher speeds. Fix both timing according
to latest DDR3 sp

driver/ddr/fsl: Fix tXP and tCKE

The driver was written using old DDR3 spec which only covers low speeds.
The value would be suboptimal for higher speeds. Fix both timing according
to latest DDR3 spec, remove tCKE as an config option.

Signed-off-by: York Sun <yorksun@freescale.com>

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# 1d71efbb 01-Aug-2014 York Sun <yorksun@freescale.com>

driver/ddr: Restruct driver to allow standalone memory space

U-boot has been initializing DDR for the main memory. The presumption
is the memory stays as a big continuous block, either linear or
int

driver/ddr: Restruct driver to allow standalone memory space

U-boot has been initializing DDR for the main memory. The presumption
is the memory stays as a big continuous block, either linear or
interleaved. This change is to support putting some DDR controllers
to separated space without counting into main memory. The standalone
memory controller could use different number of DIMM slots.

Signed-off-by: York Sun <yorksun@freescale.com>

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# 42817eb8 22-Sep-2014 Stefano Babic <sbabic@denx.de>

Merge branch 'master' of git://git.denx.de/u-boot-arm


# 8c9c74e4 10-Sep-2014 Tom Rini <trini@ti.com>

Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq


# ef87cab6 05-Sep-2014 York Sun <yorksun@freescale.com>

driver/ddr/fsl: Add support of overriding chip select write leveling

JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This
is not an issue unless some DQ pins are not connected. If

driver/ddr/fsl: Add support of overriding chip select write leveling

JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This
is not an issue unless some DQ pins are not connected. If a platform uses
regular DIMMs but with reduced DDR ECC pins, the prime DQ may end up on
those floating pins for the second rank. The workaround is to use a known
good chip select for this purpose.

Signed-off-by: York Sun <yorksun@freescale.com>

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# e7f93505 15-May-2014 Stefano Babic <sbabic@denx.de>

Merge branch 'master' of git://git.denx.de/u-boot-arm


# d2a3e911 09-May-2014 Albert ARIBAUD <albert.u.boot@aribaud.net>

Merge branch 'u-boot/master'

Conflicts:
drivers/net/Makefile

(trivial merge)


# 080d8975 25-Apr-2014 Tom Rini <trini@ti.com>

Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx


# aade2004 17-Apr-2014 Tang Yuantian <yuantian.tang@freescale.com>

mpc85xx/t104x: Add deep sleep framework support

When T104x soc wakes up from deep sleep, control is passed to the
primary core that starts executing uboot. After re-initialized some
IP blocks, like

mpc85xx/t104x: Add deep sleep framework support

When T104x soc wakes up from deep sleep, control is passed to the
primary core that starts executing uboot. After re-initialized some
IP blocks, like DDRC, kernel will take responsibility to continue
to restore environment it leaves before.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

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# 34e026f9 28-Mar-2014 York Sun <yorksun@freescale.com>

driver/ddr/fsl: Add DDR4 support to Freescale DDR driver

Mostly reusing DDR3 driver, this patch adds DDR4 SPD handling, register
calculation and programming.

Signed-off-by: York Sun <yorksun@freesc

driver/ddr/fsl: Add DDR4 support to Freescale DDR driver

Mostly reusing DDR3 driver, this patch adds DDR4 SPD handling, register
calculation and programming.

Signed-off-by: York Sun <yorksun@freescale.com>

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# 1ad6364e 05-Mar-2014 Stefano Babic <sbabic@denx.de>

Merge branch 'master' of git://git.denx.de/u-boot-arm


# 6b1e1254 10-Feb-2014 York Sun <yorksun@freescale.com>

driver/ddr: Add 256 byte interleaving support

Freescale LayerScape SoCs support controller interleaving on 256 byte size.
This interleaving is mandoratory.

Signed-off-by: York Sun <yorksun@freescal

driver/ddr: Add 256 byte interleaving support

Freescale LayerScape SoCs support controller interleaving on 256 byte size.
This interleaving is mandoratory.

Signed-off-by: York Sun <yorksun@freescale.com>

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# f15ea6e1 10-Dec-2013 Albert ARIBAUD <albert.u.boot@aribaud.net>

Merge branch 'u-boot/master' into 'u-boot-arm/master'

Conflicts:
arch/arm/cpu/armv7/rmobile/Makefile
doc/README.scrapyard

Needed manual fix:
arch/arm/cpu/armv7/omap-common/Makefile
board/compul

Merge branch 'u-boot/master' into 'u-boot-arm/master'

Conflicts:
arch/arm/cpu/armv7/rmobile/Makefile
doc/README.scrapyard

Needed manual fix:
arch/arm/cpu/armv7/omap-common/Makefile
board/compulab/cm_t335/u-boot.lds

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# 77fdd6d1 02-Dec-2013 Tom Rini <trini@ti.com>

Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx


# 5614e71b 30-Sep-2013 York Sun <yorksun@freescale.com>

Driver/DDR: Moving Freescale DDR driver to a common driver

Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs.
The similar DDR controllers will be used for ARM-based SoCs.

Signed

Driver/DDR: Moving Freescale DDR driver to a common driver

Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs.
The similar DDR controllers will be used for ARM-based SoCs.

Signed-off-by: York Sun <yorksun@freescale.com>

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