| #
b67dfc5a |
| 13-Nov-2015 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-x86
|
| #
6d41027f |
| 06-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Remove CONFIG_SYS_EARLY_PCI_INIT
CONFIG_SYS_EARLY_PCI_INIT is not needed any more since with driver
model, PCI enumeration is automatically triggered.
Signed-off-by: Bin Meng <bmeng.cn@gmail.c
x86: Remove CONFIG_SYS_EARLY_PCI_INIT
CONFIG_SYS_EARLY_PCI_INIT is not needed any more since with driver
model, PCI enumeration is automatically triggered.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
show more ...
|
| #
79c884d7 |
| 26-Aug-2015 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-x86
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| #
3ff2f001 |
| 13-Aug-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Enable CONFIG_PCI_CONFIG_HOST_BRIDGE for all boards
It looks that x86 chipset always contains a host bridge at pci
b.d.f 0.0.0, so enable this for all boards.
Signed-off-by: Bin Meng <bmeng.cn
x86: Enable CONFIG_PCI_CONFIG_HOST_BRIDGE for all boards
It looks that x86 chipset always contains a host bridge at pci
b.d.f 0.0.0, so enable this for all boards.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
show more ...
|
| #
632093b5 |
| 14-Aug-2015 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-x86
|
| #
ef910819 |
| 13-Aug-2015 |
Simon Glass <sjg@chromium.org> |
x86: minnowmax: Define and enable interrupt setup
Set up interrupts correctly so that Linux can use all devices. Use
savedefconfig to regenerate the defconfig file.
Signed-off-by: Simon Glass <sjg@
x86: minnowmax: Define and enable interrupt setup
Set up interrupts correctly so that Linux can use all devices. Use
savedefconfig to regenerate the defconfig file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
show more ...
|
| #
44a8b96f |
| 06-Aug-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: baytrail: Add all IDE/SATA PCI device IDs
The BayTrail SoC has 4 different PCI devices IDs regarding to IDE
and AHCI. Add these IDs in pci_ids.h and also add the other SATA
ID in the Bayley Bay
x86: baytrail: Add all IDE/SATA PCI device IDs
The BayTrail SoC has 4 different PCI devices IDs regarding to IDE
and AHCI. Add these IDs in pci_ids.h and also add the other SATA
ID in the Bayley Bay and MinnowMax board configuration header.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
show more ...
|
| #
1a2728ae |
| 05-Aug-2015 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-x86
|
| #
82bc22ac |
| 27-Jul-2015 |
Simon Glass <sjg@chromium.org> |
x86: minnowmax: Drop the old PCI settings
These are now in the device tree so we don't need to use the CONFIG options.
Drop them.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng
x86: minnowmax: Drop the old PCI settings
These are now in the device tree so we don't need to use the CONFIG options.
Drop them.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
show more ...
|
| #
dcfe4a54 |
| 27-Jul-2015 |
Simon Glass <sjg@chromium.org> |
x86: Move CONFIG_X86_SERIAL to Kconfig
Move this config option to Kconfig and tidy up.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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| #
456ee909 |
| 30-Jul-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: minnowmax: Remove smsc47x superio codes
On Intel BayTrail SoC, there is a legacy UART (I/O 0x3f8) integrated
into the SoC which is enabled by the FSP. Remove the smsc47x superio
initialization
x86: minnowmax: Remove smsc47x superio codes
On Intel BayTrail SoC, there is a legacy UART (I/O 0x3f8) integrated
into the SoC which is enabled by the FSP. Remove the smsc47x superio
initialization codes.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
show more ...
|
| #
4a41cc15 |
| 06-Jul-2015 |
Simon Glass <sjg@chromium.org> |
x86: minnowmax: Drop the cache line size hack
Now that the RTL8169 driver warning is fixed we can drop this. The incorrect
value is causing problems with USB EHCI.
Signed-off-by: Simon Glass <sjg@c
x86: minnowmax: Drop the cache line size hack
Now that the RTL8169 driver warning is fixed we can drop this. The incorrect
value is causing problems with USB EHCI.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
show more ...
|
| #
f448c5d3 |
| 17-Jul-2015 |
Stefano Babic <sbabic@denx.de> |
Merge branch 'master' of git://git.denx.de/u-boot
|
| #
605e15db |
| 15-Jul-2015 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-x86
|
| #
b71f9dca |
| 04-Jul-2015 |
Simon Glass <sjg@chromium.org> |
dm: x86: minnowmax: Move PCI to use driver model
Adjust minnowmax to use driver model for PCI. This requires adding a device
tree node to specify the ranges, removing the board-specific PCI code and
dm: x86: minnowmax: Move PCI to use driver model
Adjust minnowmax to use driver model for PCI. This requires adding a device
tree node to specify the ranges, removing the board-specific PCI code and
ensuring that the host bridge is configured.
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
show more ...
|
| #
d5359f2e |
| 04-Jul-2015 |
Simon Glass <sjg@chromium.org> |
dm: spi: Enable environment for minnowmax
Enable a SPI environment and store it in a suitable place.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewe
dm: spi: Enable environment for minnowmax
Enable a SPI environment and store it in a suitable place.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Jagan Teki <jteki@openedev.com>
show more ...
|
| #
786a08e0 |
| 06-Jul-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Move VGA option rom macros to Kconfig
Move X86_OPTION_ROM_FILE & X86_OPTION_ROM_ADDR to arch/x86/Kconfig
and rename them to VGA_BIOS_FILE & VGA_BIOS_ADDR which depend on
HAVE_VGA_BIOS. The new
x86: Move VGA option rom macros to Kconfig
Move X86_OPTION_ROM_FILE & X86_OPTION_ROM_ADDR to arch/x86/Kconfig
and rename them to VGA_BIOS_FILE & VGA_BIOS_ADDR which depend on
HAVE_VGA_BIOS. The new names are consistent with other x86 binary
blob options like HAVE_FSP/FSP_FILE/FSP_ADDR.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
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|
| #
6f43ba70 |
| 07-Jul-2015 |
Albert ARIBAUD <albert.u.boot@aribaud.net> |
Merge branch 'u-boot/master' into 'u-boot-arm/master'
|
| #
5d3c2c54 |
| 12-May-2015 |
Gabriel Huau <contact@huau-gabriel.fr> |
x86: minnowmax: initialize the pin-muxing from device tree
Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
Acked-by: Simon Glass <sjg@chromium.org>
|
| #
6bde2dc5 |
| 10-May-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Move FRAMEBUFFER_SET_VESA_MODE etc to video Kconfig
CONFIG_FRAMEBUFFER_SET_VESA_MODE and CONFIG_FRAMEBUFFER_VESA_MODE
are not x86-specific, so move them to drivers/video/Kconfig and
make them d
x86: Move FRAMEBUFFER_SET_VESA_MODE etc to video Kconfig
CONFIG_FRAMEBUFFER_SET_VESA_MODE and CONFIG_FRAMEBUFFER_VESA_MODE
are not x86-specific, so move them to drivers/video/Kconfig and
make them depend on VIDEO_VESA driver. Some cosmetic fixes are
applied to the Kconfig help text as well.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
show more ...
|
| #
3d5bbbc4 |
| 07-May-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Set CONFIG_NR_DRAM_BANKS to 8 and move it to x86-common.h
Some x86 boards set CONFIG_NR_DRAM_BANKS to 1, which causes incorrect
DRAM size printed when booting from coreboot, like this:
CPU: x
x86: Set CONFIG_NR_DRAM_BANKS to 8 and move it to x86-common.h
Some x86 boards set CONFIG_NR_DRAM_BANKS to 1, which causes incorrect
DRAM size printed when booting from coreboot, like this:
CPU: x86, vendor Intel, device 663h
DRAM: 636 KiB
Using default environment
Change it to 8 which should be enough for both coreboot and bare
cases, and move it to x86-common.h.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
show more ...
|
| #
8ddb8cfb |
| 25-Apr-2015 |
Gabriel Huau <contact@huau-gabriel.fr> |
x86: minnowmax: use the correct NOR in the configuration
The SPI NOR on the minnowboard max is a MICRON N25Q064A
Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
Reviewed-by: Bin Meng <bmeng.c
x86: minnowmax: use the correct NOR in the configuration
The SPI NOR on the minnowboard max is a MICRON N25Q064A
Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
show more ...
|
| #
d21d05f1 |
| 31-Mar-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Move CONFIG_ENV_IS_IN_SPI_FLASH to x86-common.h
Since all x86 boards use spi flash as its bootloader storage media,
it makes sense to make CONFIG_ENV_IS_IN_SPI_FLASH a common option.
So far onl
x86: Move CONFIG_ENV_IS_IN_SPI_FLASH to x86-common.h
Since all x86 boards use spi flash as its bootloader storage media,
it makes sense to make CONFIG_ENV_IS_IN_SPI_FLASH a common option.
So far only minnowmax board does not support it so undefine it in
its board configuration file.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
show more ...
|
| #
e1cc4d31 |
| 24-Feb-2015 |
Albert ARIBAUD <albert.u.boot@aribaud.net> |
Merge remote-tracking branch 'u-boot/master' into 'u-boot-arm/master'
|
| #
e72d3443 |
| 13-Feb-2015 |
Stefano Babic <sbabic@denx.de> |
Merge branch 'master' of git://git.denx.de/u-boot
|