| #
4dd02a75 |
| 24-Aug-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: crownbay: Enable on-board SMSC superio keyboard controller
So far we only enabled one legacy serial port on the SMSC LPC47m
superio chipset on Intel Crown Bay board. As the board also has
dual
x86: crownbay: Enable on-board SMSC superio keyboard controller
So far we only enabled one legacy serial port on the SMSC LPC47m
superio chipset on Intel Crown Bay board. As the board also has
dual PS/2 ports routed out, enable the keyboard controller which
is i8042 compatible so that we can use PS/2 keyboard and mouse.
In order to make PS/2 keyboard work with the VGA console, remove
CONFIG_VGA_AS_SINGLE_DEVICE. To boot Linux kernel with PIC mode
using PIRQ routing table, adjust the mask in the device tree to
reserve irq12 which is used by PS/2 mouse.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
show more ...
|
| #
3ff2f001 |
| 13-Aug-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Enable CONFIG_PCI_CONFIG_HOST_BRIDGE for all boards
It looks that x86 chipset always contains a host bridge at pci
b.d.f 0.0.0, so enable this for all boards.
Signed-off-by: Bin Meng <bmeng.cn
x86: Enable CONFIG_PCI_CONFIG_HOST_BRIDGE for all boards
It looks that x86 chipset always contains a host bridge at pci
b.d.f 0.0.0, so enable this for all boards.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
show more ...
|
| #
14e7a30f |
| 24-Aug-2015 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-net
|
| #
a77fda1f |
| 19-Aug-2015 |
Simon Glass <sjg@chromium.org> |
net: Move CONFIG_E1000 options to Kconfig
Move config for the E1000 Ethernet driver to Kconfig and tidy up affected
boards.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <
net: Move CONFIG_E1000 options to Kconfig
Move config for the E1000 Ethernet driver to Kconfig and tidy up affected
boards.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
show more ...
|
| #
1a2728ae |
| 05-Aug-2015 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-x86
|
| #
dcfe4a54 |
| 27-Jul-2015 |
Simon Glass <sjg@chromium.org> |
x86: Move CONFIG_X86_SERIAL to Kconfig
Move this config option to Kconfig and tidy up.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
|
| #
f448c5d3 |
| 17-Jul-2015 |
Stefano Babic <sbabic@denx.de> |
Merge branch 'master' of git://git.denx.de/u-boot
|
| #
605e15db |
| 15-Jul-2015 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-x86
|
| #
7aaff9bf |
| 06-Jul-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: crownbay: Enable graphics support
Enable graphics support on Intel Crown Bay board With the help of
vgabios for Intel TunnelCreek IGD. Tested with an external LVDS
panel connected to X4 connect
x86: crownbay: Enable graphics support
Enable graphics support on Intel Crown Bay board With the help of
vgabios for Intel TunnelCreek IGD. Tested with an external LVDS
panel connected to X4 connector and SDVO adapter connected to X9
connector on the board.
Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
show more ...
|
| #
6f43ba70 |
| 07-Jul-2015 |
Albert ARIBAUD <albert.u.boot@aribaud.net> |
Merge branch 'u-boot/master' into 'u-boot-arm/master'
|
| #
3d5bbbc4 |
| 07-May-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Set CONFIG_NR_DRAM_BANKS to 8 and move it to x86-common.h
Some x86 boards set CONFIG_NR_DRAM_BANKS to 1, which causes incorrect
DRAM size printed when booting from coreboot, like this:
CPU: x
x86: Set CONFIG_NR_DRAM_BANKS to 8 and move it to x86-common.h
Some x86 boards set CONFIG_NR_DRAM_BANKS to 1, which causes incorrect
DRAM size printed when booting from coreboot, like this:
CPU: x86, vendor Intel, device 663h
DRAM: 636 KiB
Using default environment
Change it to 8 which should be enough for both coreboot and bare
cases, and move it to x86-common.h.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
show more ...
|
| #
afbf1404 |
| 24-Apr-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: queensbay: Implement PIRQ routing
Implement Intel Queensbay platform-specific PIRQ routing support.
The chipset PIRQ routing setup is called in the arch_misc_init().
Signed-off-by: Bin Meng <b
x86: queensbay: Implement PIRQ routing
Implement Intel Queensbay platform-specific PIRQ routing support.
The chipset PIRQ routing setup is called in the arch_misc_init().
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
show more ...
|
| #
d21d05f1 |
| 31-Mar-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Move CONFIG_ENV_IS_IN_SPI_FLASH to x86-common.h
Since all x86 boards use spi flash as its bootloader storage media,
it makes sense to make CONFIG_ENV_IS_IN_SPI_FLASH a common option.
So far onl
x86: Move CONFIG_ENV_IS_IN_SPI_FLASH to x86-common.h
Since all x86 boards use spi flash as its bootloader storage media,
it makes sense to make CONFIG_ENV_IS_IN_SPI_FLASH a common option.
So far only minnowmax board does not support it so undefine it in
its board configuration file.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
show more ...
|
| #
b491d975 |
| 10-Apr-2015 |
Albert ARIBAUD <albert.u.boot@aribaud.net> |
Merge branch 'u-boot/master'
|
| #
10af8781 |
| 27-Mar-2015 |
Tom Rini <trini@konsulko.com> |
Merge branch 'master' of git://git.denx.de/u-boot-x86
|
| #
fba02d69 |
| 11-Mar-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: crownbay: Enable saving environment in SPI flash
Saving U-Boot's environment in SPI flash on Intel CrownBay board.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sg@chromi
x86: crownbay: Enable saving environment in SPI flash
Saving U-Boot's environment in SPI flash on Intel CrownBay board.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sg@chromium.org>
show more ...
|
| #
a84134f7 |
| 20-Mar-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: crownbay: Enable Intel Topcliff GMAC support
Intel Crown Bay board has one ethernet port connected from Intel
Topcliff PCH. Enable it in the board configuration.
Signed-off-by: Bin Meng <bmeng
x86: crownbay: Enable Intel Topcliff GMAC support
Intel Crown Bay board has one ethernet port connected from Intel
Topcliff PCH. Enable it in the board configuration.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
show more ...
|
| #
5f88ed5c |
| 13-Jan-2015 |
Tom Rini <trini@ti.com> |
Merge git://git.denx.de/u-boot-x86
|
| #
8cb20ccc |
| 06-Jan-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Move CONFIG_X86_RESET_VECTOR and CONFIG_SYS_X86_START16 to Kconfig
Convert CONFIG_X86_RESET_VECTOR and CONFIG_SYS_X86_START16 to Kconfig
options so that we can remove them from board configurat
x86: Move CONFIG_X86_RESET_VECTOR and CONFIG_SYS_X86_START16 to Kconfig
Convert CONFIG_X86_RESET_VECTOR and CONFIG_SYS_X86_START16 to Kconfig
options so that we can remove them from board configuration file.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
show more ...
|
| #
4e0114d9 |
| 30-Dec-2014 |
Stefano Babic <sbabic@denx.de> |
Merge branch 'master' of git://git.denx.de/u-boot
Signed-off-by: Stefano Babic <sbabic@denx.de>
|
| #
d8046ff0 |
| 19-Dec-2014 |
Tom Rini <trini@ti.com> |
Merge git://git.denx.de/u-boot-x86
|
| #
41702bac |
| 17-Dec-2014 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Rename coreboot-serial to x86-serial
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
|
| #
aada6276 |
| 17-Dec-2014 |
Bin Meng <bmeng.cn@gmail.com> |
x86: crownbay: Add SDHCI support
There are two standard SD card slots on the Crown Bay board, which
are connected to the Topcliff PCH SDIO controllers. Enable the SDHC
support so that we can use the
x86: crownbay: Add SDHCI support
There are two standard SD card slots on the Crown Bay board, which
are connected to the Topcliff PCH SDIO controllers. Enable the SDHC
support so that we can use them.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
show more ...
|
| #
0ff65eb9 |
| 17-Dec-2014 |
Bin Meng <bmeng.cn@gmail.com> |
x86: crownbay: Enable Intel E1000 NIC support
We don't have driver for the Intel Topcliff PCH Gigabit Ethernet
controller for now, so enable the Intle E1000 NIC support, which
can be plugged into an
x86: crownbay: Enable Intel E1000 NIC support
We don't have driver for the Intel Topcliff PCH Gigabit Ethernet
controller for now, so enable the Intle E1000 NIC support, which
can be plugged into any PCIe slot on the Crown Bay board.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
show more ...
|
| #
adfe3b24 |
| 17-Dec-2014 |
Bin Meng <bmeng.cn@gmail.com> |
x86: crownbay: Add SPI flash support
The Crown Bay board has an SST25VF016B flash connected to the Tunnel
Creek processor SPI controller used as the BIOS media where U-Boot
is stored. Enable this fl
x86: crownbay: Add SPI flash support
The Crown Bay board has an SST25VF016B flash connected to the Tunnel
Creek processor SPI controller used as the BIOS media where U-Boot
is stored. Enable this flash support.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
show more ...
|