| #
677f970b |
| 09-Sep-2015 |
Gong Qianyu <Qianyu.Gong@freescale.com> |
common/board_f.c: modify the macro to use get_clocks() more common
get_clocks() should not be limited by ESDHC.
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com>
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| #
1254ff97 |
| 10-Jul-2015 |
Stefano Babic <sbabic@denx.de> |
Merge branch 'master' of git://git.denx.de/u-boot
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| #
6f43ba70 |
| 07-Jul-2015 |
Albert ARIBAUD <albert.u.boot@aribaud.net> |
Merge branch 'u-boot/master' into 'u-boot-arm/master'
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| #
c9bb942e |
| 22-Jun-2015 |
Joe Hershberger <joe.hershberger@ni.com> |
Move default y configs out of arch/board Kconfig
Some archs/boards specify their own default by pre-defining the config which causes the Kconfig system to mix up the order of the configs in the defc
Move default y configs out of arch/board Kconfig
Some archs/boards specify their own default by pre-defining the config which causes the Kconfig system to mix up the order of the configs in the defconfigs... This will cause merge pain if allowed to proliferate.
Remove the configs that behave this way from the archs.
A few configs still remain, but that is because they only exist as defaults and do not have a proper Kconfig entry. Those appear to be:
SPIFLASH DISPLAY_BOARDINFO
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> [trini: rastaban, am43xx_evm_usbhost_boot, am43xx_evm_ethboot updates, drop DM_USB from MSI_Primo81 as USB_MUSB_SUNXI isn't converted yet to DM] Signed-off-by: Tom Rini <trini@konsulko.com>
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| #
b491d975 |
| 10-Apr-2015 |
Albert ARIBAUD <albert.u.boot@aribaud.net> |
Merge branch 'u-boot/master'
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| #
482cbd55 |
| 31-Mar-2015 |
Tom Rini <trini@konsulko.com> |
Merge git://git.denx.de/u-boot-nand-flash
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| #
073adf98 |
| 03-Feb-2015 |
Peter Tyser <ptyser@xes-inc.com> |
nand: Remove CONFIG_MTD_NAND_VERIFY_WRITE
The CONFIG_MTD_NAND_VERIFY_WRITE has been removed from Linux for some time and a more generic method of NAND verification now exists in U-Boot.
Signed-off-
nand: Remove CONFIG_MTD_NAND_VERIFY_WRITE
The CONFIG_MTD_NAND_VERIFY_WRITE has been removed from Linux for some time and a more generic method of NAND verification now exists in U-Boot.
Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Tested-by: Heiko Schocher <hs@denx.de> Acked-by: Heiko Schocher <hs@denx.de>
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| #
e3bf81b1 |
| 16-Dec-2014 |
Tom Rini <trini@ti.com> |
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
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| #
3fa66db4 |
| 08-Dec-2014 |
Jeffrey Ladouceur <Jeffrey.Ladouceur@freescale.com> |
mpc85xx: inhibit qman and bman portals by default
Not all portals might be managed and therefore visible. Set the isdr register so that the corresponding isr register won't be set. This is required
mpc85xx: inhibit qman and bman portals by default
Not all portals might be managed and therefore visible. Set the isdr register so that the corresponding isr register won't be set. This is required when supporting power management.
Signed-off-by: Jeffrey Ladouceur <Jeffrey.Ladouceur@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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| #
a84c8107 |
| 20-Oct-2014 |
Tom Rini <trini@ti.com> |
Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq
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| #
789490b6 |
| 07-Oct-2014 |
Ruchika Gupta <ruchika.gupta@freescale.com> |
mpc85xx: configs - Enable blob command in freescale platforms
Enable blob commands for platforms having SEC 4.0 or greater for secure boot scenarios
Signed-off-by: Ruchika Gupta <ruchika.gupta@free
mpc85xx: configs - Enable blob command in freescale platforms
Enable blob commands for platforms having SEC 4.0 or greater for secure boot scenarios
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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| #
737537ef |
| 15-Oct-2014 |
Ruchika Gupta <ruchika.gupta@freescale.com> |
mpc85xx: configs - Add hash command in freescale platforms
Enable CAAM in platforms supporting the hardware block. Hash command enabled along with hardware accelerated support for SHA-1 and SHA-256
mpc85xx: configs - Add hash command in freescale platforms
Enable CAAM in platforms supporting the hardware block. Hash command enabled along with hardware accelerated support for SHA-1 and SHA-256 for platforms which have CAAM block.
Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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| #
e82abaeb |
| 11-Aug-2014 |
Stefano Babic <sbabic@denx.de> |
Merge branch 'master' of git://git.denx.de/u-boot-arm
Conflicts: boards.cfg
Signed-off-by: Stefano Babic <sbabic@denx.de>
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| #
25b4adbb |
| 30-Jul-2014 |
Masahiro Yamada <yamada.m@jp.panasonic.com> |
include: remove CONFIG_SPL/CONFIG_TPL definition in config headers
Now CONFIG_SPL and CONFIG_TPL are defined in Kconfig.
Remove the redundant definition in config headers.
Signed-off-by: Masahiro
include: remove CONFIG_SPL/CONFIG_TPL definition in config headers
Now CONFIG_SPL and CONFIG_TPL are defined in Kconfig.
Remove the redundant definition in config headers.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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| #
4ce99570 |
| 30-Jul-2014 |
Masahiro Yamada <yamada.m@jp.panasonic.com> |
include: define CONFIG_SPL and CONFIG_TPL as 1
We are about to switch to Kconfig in the next commit. But there are something to get done beforehand.
In Kconfig, include/generated/autoconf.h defines
include: define CONFIG_SPL and CONFIG_TPL as 1
We are about to switch to Kconfig in the next commit. But there are something to get done beforehand.
In Kconfig, include/generated/autoconf.h defines boolean CONFIG macros as 1.
CONFIG_SPL and CONFIG_TPL, if defined, must be set to 1. Otherwise, when switching to Kconfig, the build log would be sprinkled with warning messages like this: warning: "CONFIG_SPL" redefined [enabled by default]
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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| #
d5f8a6dd |
| 28-Jul-2014 |
Tom Rini <trini@ti.com> |
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
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| #
de519163 |
| 26-Jun-2014 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
powerpc/ifc: fix invalid CSn FTIM2.TCH setting
On some platforms, CSn FTIM2.TCH is set to zero which is invalid, an invalid hold time makes DUT timing variances, whether it works or not on luck.
Si
powerpc/ifc: fix invalid CSn FTIM2.TCH setting
On some platforms, CSn FTIM2.TCH is set to zero which is invalid, an invalid hold time makes DUT timing variances, whether it works or not on luck.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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| #
05d134b0 |
| 20-May-2014 |
Albert ARIBAUD <albert.u.boot@aribaud.net> |
Merge remote-tracking branch 'u-boot/master'
Conflicts: boards.cfg
Conflicts were trivial once u-boot-arm/master boards.cfg was reformatted (commit 6130c146) to match u-boot/master's own reformatt
Merge remote-tracking branch 'u-boot/master'
Conflicts: boards.cfg
Conflicts were trivial once u-boot-arm/master boards.cfg was reformatted (commit 6130c146) to match u-boot/master's own reformatting (commit 1b37fa83).
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| #
d7782d06 |
| 16-May-2014 |
Tom Rini <trini@ti.com> |
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
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| #
e4911815 |
| 15-May-2014 |
Liu Gang <Gang.Liu@freescale.com> |
powerpc/srio-pcie-boot: Adjust addresses for SRIO/PCIE boot
The new 768KB u-boot image size requires changes for SRIO/PCIE boot. These addresses need to be updated to appropriate locations.
The upd
powerpc/srio-pcie-boot: Adjust addresses for SRIO/PCIE boot
The new 768KB u-boot image size requires changes for SRIO/PCIE boot. These addresses need to be updated to appropriate locations.
The updated addresses are used to configure the SRIO/PCIE inbound windows for the boot, and they must be aligned with the window size based on the SRIO/PCIE modules requirement. So for the 768KB u-boot image, the inbound window cannot be set with 0xfff40000 base address and 0xc0000 size, it should be extended to 1MB size and the base address can be aligned with the size.
Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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| #
3246584d |
| 15-May-2014 |
Kim Phillips <kim.phillips@freescale.com> |
mpc85xx: configs: remove c=ffe from default environment
AFAICT, c=ffe does nothing and was a typo from the original commit d17123696c6180ac8b74fbd318bf14652623e982 "powerpc/p4080: Add support for th
mpc85xx: configs: remove c=ffe from default environment
AFAICT, c=ffe does nothing and was a typo from the original commit d17123696c6180ac8b74fbd318bf14652623e982 "powerpc/p4080: Add support for the P4080DS board" and just kept on getting duplicated in subsequently added board config files.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Acked-by: Edward Swarthout <ed.swarthout@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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| #
e7f93505 |
| 15-May-2014 |
Stefano Babic <sbabic@denx.de> |
Merge branch 'master' of git://git.denx.de/u-boot-arm
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| #
d2a3e911 |
| 09-May-2014 |
Albert ARIBAUD <albert.u.boot@aribaud.net> |
Merge branch 'u-boot/master'
Conflicts: drivers/net/Makefile
(trivial merge)
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| #
080d8975 |
| 25-Apr-2014 |
Tom Rini <trini@ti.com> |
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
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| #
b6036993 |
| 22-Apr-2014 |
Shaohui Xie <Shaohui.Xie@freescale.com> |
powerpc/T4QDS: add two stage boot of nand/sd
Add support of 2 stage NAND/SD boot loader using SPL framework. PBL initialise the internal SRAM and copy SPL, this further initialise DDR using SPD and
powerpc/T4QDS: add two stage boot of nand/sd
Add support of 2 stage NAND/SD boot loader using SPL framework. PBL initialise the internal SRAM and copy SPL, this further initialise DDR using SPD and environment and copy u-boot from NAND/SD to DDR, finally SPL transfer control to u-boot. NOR uses CS1 instead of CS2 when NAND boot, fix it.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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