| 7e72214d | 28-Mar-2019 |
Shixiang Zheng <shixiang.zheng@rock-chips.com> |
video/drm: logo: the negative height will cause vop register err
the bmp file has been processed when reserved equals BMP_PROCESSED_FLAG
Change-Id: I793582cdd4ee5ee2a774c7a0dee8d36c81ed4f4c
Signed-
video/drm: logo: the negative height will cause vop register err
the bmp file has been processed when reserved equals BMP_PROCESSED_FLAG
Change-Id: I793582cdd4ee5ee2a774c7a0dee8d36c81ed4f4c
Signed-off-by: Shixiang Zheng <shixiang.zheng@rock-chips.com>
show more ...
|
| 005d29a7 | 04-Mar-2019 |
Wyon Bi <bivvy.bi@rock-chips.com> |
video/drm: rockchip_display: support get display mode from edid if client is not present
Change-Id: Ib8956972b7bbb6aaaac2e3c8a93e0d38d98abf6a
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com> |
| cf0aae68 | 19-Feb-2019 |
Wyon Bi <bivvy.bi@rock-chips.com> |
video/drm: rk618_lvds: Add support for MEDIA_BUS_FMT_RGB666_1X7X3_JEIDA bus format
Change-Id: I12480932e3f5fa6ea1dc4684be697989eff304fc
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com> |
| 9c5e1148 | 18-Feb-2019 |
Wyon Bi <bivvy.bi@rock-chips.com> |
video/drm: vop: Add support lvds bus format
Change-Id: I9674d3478d279f0e0fd47529f96d336c4027cd13
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com> |
| 4888f8a4 | 18-Feb-2019 |
Wyon Bi <bivvy.bi@rock-chips.com> |
video/drm: lvds: Add support for MEDIA_BUS_FMT_RGB666_1X7X3_JEIDA bus format
Change-Id: Id8b17e482036ce7c8eb543a673eb1b745958c7c3
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com> |
| 31018a86 | 18-Feb-2019 |
Wyon Bi <bivvy.bi@rock-chips.com> |
video/drm: lvds: Correct P2S_EN register field on px30
Change-Id: I464df20abe7a3fb1d1fb5f275a9c79a672008a96
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com> |
| db7863d0 | 15-Feb-2019 |
Wyon Bi <bivvy.bi@rock-chips.com> |
video/drm: lvds: Remove unused file
Change-Id: If7398e132de477079a366e0b1df82b83856e9b05
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com> |
| 1953e619 | 31-Jan-2019 |
Wyon Bi <bivvy.bi@rock-chips.com> |
video/drm: Sync MIPI DSI Bus helper from Linux 4.9
This imports drivers/gpu/drm/drm_mipi_dsi.c from Linux kernel 4.9.
It can be very helpful when porting Linux mipi dsi driver to U-Boot.
DSI hosts
video/drm: Sync MIPI DSI Bus helper from Linux 4.9
This imports drivers/gpu/drm/drm_mipi_dsi.c from Linux kernel 4.9.
It can be very helpful when porting Linux mipi dsi driver to U-Boot.
DSI hosts expose operations which can be used by DSI peripheral drivers
to access associated devices.
Change-Id: Iccfa9d946f33458867f4d4db0ce04aeb1918e855
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
show more ...
|
| 85e15df9 | 31-Jan-2019 |
Wyon Bi <bivvy.bi@rock-chips.com> |
video/drm: Rename rockchip-inno-mipi-dphy.c to inno_mipi_phy.c
Change-Id: I20b9c24fc7df3f4fb74eb8ce7b722b945ac7d245
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com> |
| dddde95b | 30-Jan-2019 |
Wyon Bi <bivvy.bi@rock-chips.com> |
video/drm: analogix_dp: add edp reset control support
This patch adds eDP software reset operation to make sure
register access successfully on RK3288 and it fixes possible
register default value ab
video/drm: analogix_dp: add edp reset control support
This patch adds eDP software reset operation to make sure
register access successfully on RK3288 and it fixes possible
register default value abnormal issue during boot up.
1) normal case:
Rockchip UBOOT DRM driver version: v1.0.1
0x120: 0x00000007
0x390: 0x00000003
Using display timing dts
Detailed mode clock 200000 kHz, flags[a]
H: 1536 1548 1564 1612
V: 2048 2056 2060 2068
bus_format: 100e
Link Training success!
final link rate = 0x06, lane count = 0x04
2) abnormal case:
Rockchip UBOOT DRM driver version: v1.0.1
0x120: 0x00000066
0x390: 0x00000202
Using display timing dts
Detailed mode clock 200000 kHz, flags[a]
H: 1536 1548 1564 1612
V: 2048 2056 2060 2068
bus_format: 100e
failed to get Rx Max Link Rate
failed to init training
unable to do link train
Change-Id: Idacbb0c72a40442da3a87e60bfe1d9965f3ca79c
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
show more ...
|
| 611de317 | 28-Jan-2019 |
Wyon Bi <bivvy.bi@rock-chips.com> |
video/drm: analogix_dp: Fix color depth configuration
Change-Id: Iea7fb59a2eb811d3db09cb6d0d8be03cd98a4645
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com> |
| 00cdbd6c | 28-Jan-2019 |
Wyon Bi <bivvy.bi@rock-chips.com> |
video/drm: panel: Allow to configure bpc (bits per color) from DT
Change-Id: Iad86b7121e4cdfbd981daba6f860fd8b97bca52a
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com> |
| 74e39389 | 30-Jan-2019 |
Wyon Bi <bivvy.bi@rock-chips.com> |
video/drm: Rename rockchip-dw-mipi-dsi.c to dw_mipi_dsi.c
Change-Id: I409b32e945a2182e2948255b02644a98d16fcc21
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com> |
| 8b8b9c4b | 30-Jan-2019 |
Wyon Bi <bivvy.bi@rock-chips.com> |
video/drm: dsi: fix pll clock setting for synopsys phy
Fixes: 1c3c799444b5 ("video/drm: dsi: fix pll clock setting for synopsys phy")
Change-Id: I1b5ef22c6c63a99dd3f10ea03f31d50d3bfeea06
Signed-off-
video/drm: dsi: fix pll clock setting for synopsys phy
Fixes: 1c3c799444b5 ("video/drm: dsi: fix pll clock setting for synopsys phy")
Change-Id: I1b5ef22c6c63a99dd3f10ea03f31d50d3bfeea06
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
show more ...
|
| 49ae8667 | 24-Jan-2019 |
Wyon Bi <bivvy.bi@rock-chips.com> |
video/drm: display: atomic display enable handling
Change-Id: If71e8590fb4e1b1e743d4b085e42b7530f518084
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com> |
| 9f1d10d3 | 19-Jan-2019 |
Wyon Bi <bivvy.bi@rock-chips.com> |
video/drm: dsi: rework dual channel mode
Change-Id: If119532a057d731f523a7ec8b035e9addc76d1e1
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com> |
| 1c3c7994 | 19-Jan-2019 |
Wyon Bi <bivvy.bi@rock-chips.com> |
video/drm: dsi: fix pll clock setting for synopsys phy
Change-Id: Ib2cfdf413e3c4da039a16971fcc00baaab3b101c
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
(sync from rk/kernel:develop-4.4:331690a1
video/drm: dsi: fix pll clock setting for synopsys phy
Change-Id: Ib2cfdf413e3c4da039a16971fcc00baaab3b101c
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
(sync from rk/kernel:develop-4.4:331690a183f536fe8a791ceed4231f7e484f8fb7)
show more ...
|
| cef5be6b | 19-Jan-2019 |
Wyon Bi <bivvy.bi@rock-chips.com> |
video/drm: dsi: Bypass TLP clock lane and data lanes counter threshold
Change-Id: I2b750800859626f3d95ebe6b1b8a3d86aefc07d1
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
(sync from rk/kernel:deve
video/drm: dsi: Bypass TLP clock lane and data lanes counter threshold
Change-Id: I2b750800859626f3d95ebe6b1b8a3d86aefc07d1
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
(sync from rk/kernel:develop-4.4:3ef4c2204f9be3f0877333b5d35ab11e322ed90d)
show more ...
|
| 2612c820 | 19-Jan-2019 |
Wyon Bi <bivvy.bi@rock-chips.com> |
video/drm: dsi: Don't hardcode/bypass phy default parameters
Change-Id: If8670bee99c1397647323b34acd3e3da028549c3
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
(sync from rk/kernel:develop-4.4:bd
video/drm: dsi: Don't hardcode/bypass phy default parameters
Change-Id: If8670bee99c1397647323b34acd3e3da028549c3
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
(sync from rk/kernel:develop-4.4:bd920c36fc56d00a24d3688510c84c62d7921c6a)
show more ...
|
| 374e7550 | 19-Jan-2019 |
Wyon Bi <bivvy.bi@rock-chips.com> |
video/drm: dsi: fix phy power-on sequence
Change-Id: I1f48f5d13d772ee8c3c71ee40f122811d687bcc6
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
(sync from rk/kernel:develop-4.4:1df398e95a19c472ac847
video/drm: dsi: fix phy power-on sequence
Change-Id: I1f48f5d13d772ee8c3c71ee40f122811d687bcc6
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
(sync from rk/kernel:develop-4.4:1df398e95a19c472ac847ced671175f147a043ad)
show more ...
|
| e6cbaa24 | 19-Jan-2019 |
Wyon Bi <bivvy.bi@rock-chips.com> |
video/drm: dsi: rework test interface
Change-Id: I8521fa8aa8b1ba11888dd506f238e6e6c2d7ad39
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
(sync from rk/kernel:develop-4.4:2c659c75a6fb5fc99279a8d4e
video/drm: dsi: rework test interface
Change-Id: I8521fa8aa8b1ba11888dd506f238e6e6c2d7ad39
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
(sync from rk/kernel:develop-4.4:2c659c75a6fb5fc99279a8d4e64b222d0158e77b)
show more ...
|
| 2400e5a4 | 22-Jan-2019 |
Wyon Bi <bivvy.bi@rock-chips.com> |
video/drm: Kconfig: select generic phy by default
Change-Id: I07fa63bfc1e03ed87c78555cb96d106c603d083a
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com> |
| 513e5cb6 | 08-Jan-2019 |
Sandy Huang <hjc@rock-chips.com> |
drm/rockchip: vop: add hdmi pol config for px3se
if miss this commit will appear hdmi display abnormal at
some TV.
Change-Id: I86f1425135ccf5fb53c0373ad6d070e1f6efe66d
Signed-off-by: Sandy Huang <h
drm/rockchip: vop: add hdmi pol config for px3se
if miss this commit will appear hdmi display abnormal at
some TV.
Change-Id: I86f1425135ccf5fb53c0373ad6d070e1f6efe66d
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
show more ...
|
| b69d3ed4 | 28-Dec-2018 |
Wyon Bi <bivvy.bi@rock-chips.com> |
video/drm: lvds: Clean up phy code
The video phy of px30/rk3128/rk3288/rk3368 is now supported by
inno_video_combo_phy.c/inno_video_phy.c in directory drviers/video/drm.
Change-Id: I5471de3aa7c43fb
video/drm: lvds: Clean up phy code
The video phy of px30/rk3128/rk3288/rk3368 is now supported by
inno_video_combo_phy.c/inno_video_phy.c in directory drviers/video/drm.
Change-Id: I5471de3aa7c43fbf379b4313f158038145ab36c1
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
show more ...
|
| 49627130 | 28-Dec-2018 |
Wyon Bi <bivvy.bi@rock-chips.com> |
video/drm: rgb: Add support for rk3128/rk3288/rk3368
Change-Id: I248a2966514f4417d88c070dcb4e87e682f04df5
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com> |