| 52db8715 | 11-Nov-2019 |
Wyon Bi <bivvy.bi@rock-chips.com> |
video/drm: analogix_dp: Workaround async issue between pclk clock and 24m clock
Background:
- EDP software register bank is on the EDP 24m clock domain;
- CPU access EDP software register bank, need
video/drm: analogix_dp: Workaround async issue between pclk clock and 24m clock
Background:
- EDP software register bank is on the EDP 24m clock domain;
- CPU access EDP software register bank, need to go through EDP APB
read/write bus and EDP internal read/write bus;
- EDP APB read/write bus is on the EDP pclk clock domain;
- EDP internal read/write bus is on the EDP 24m clock domain;
- Asynchronous logic circuit is added between APB read/write bus and
Internal read/write bus;
Issue:
There is a bug on the Asynchronous logic circuit between APB read/write
bus and Internal read/write bus; This bug will be random to cause the
following wrong control/address signals sequence happen;
- For write, maybe wrong register address is wrote in;
- For read, maybe wrong register address is read out;
Workaround:
- For CPU write EDP register operation, write any register need
following three steps,
1): Read EDP_BASE+0x00 dummy register firstly, latch the dummy
register address on Reg_Address bus, to avoid next step write to
wrong register to cause function register overrun;
2): 1st time to write the EDP register you want to operate,
to latch the real write address on Reg_Address bus;
3): 2nd time to write the EDP register you want to operate,
to make sure the data is write on the real write address;
- For CPU read EDP register operation, read any register need following
two steps,
1): 1st time to read the EDP register you want to operate, to latch
the real read address on Reg_Address bus;
2): 2nd time to read the EDP register you want to operate, to make
sure the data is read out from the real read address;
Change-Id: I42613145b1d414321ac1aef290a35969a1461e36
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
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| 75eb6fce | 16-Sep-2019 |
Algea Cao <algea.cao@rock-chips.com> |
video/drm: Add bridge get_timing interface
Some bridge can't get tv edid such as rk1000 cvbs, but
at present bridge can't provide timing without edid. So
we add get_timing interface to provide timin
video/drm: Add bridge get_timing interface
Some bridge can't get tv edid such as rk1000 cvbs, but
at present bridge can't provide timing without edid. So
we add get_timing interface to provide timing.
Change-Id: Id74802a3bff8140e3677f6633788aacd021afc91
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
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| 3320fa93 | 24-Jul-2019 |
Wyon Bi <bivvy.bi@rock-chips.com> |
video/drm: dsi: resolved dependency between mipi_tx0 and mipi_tx1
It has a shared pll for mipi_tx0/mipi_tx1 on RK3288/RK3399,
so we need to initialize mipi_tx0 as necessary before enabling mipi_tx1.
video/drm: dsi: resolved dependency between mipi_tx0 and mipi_tx1
It has a shared pll for mipi_tx0/mipi_tx1 on RK3288/RK3399,
so we need to initialize mipi_tx0 as necessary before enabling mipi_tx1.
Change-Id: I217c93232c6cfdfb7bf15142b903d44783120ab0
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
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| 19c2faf2 | 18-Jul-2019 |
Algea Cao <algea.cao@rock-chips.com> |
drm/rockchip: dw-hdmi: Fix hdmi i2c scl configuration error
If ddc-i2c-scl-high-time-ns and ddc-i2c-scl-low-time-ns are not
set in dts, scl_high_ns and scl_low_ns will set to -1. Because of
these va
drm/rockchip: dw-hdmi: Fix hdmi i2c scl configuration error
If ddc-i2c-scl-high-time-ns and ddc-i2c-scl-low-time-ns are not
set in dts, scl_high_ns and scl_low_ns will set to -1. Because of
these variables are unsigned int, misjudgment may occur when their
values are judged.
Change-Id: I8b94f7c2ab8bcb0d966182f220877f9268b7981b
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
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| 3f6d16ab | 09-Jul-2019 |
Algea Cao <algea.cao@rock-chips.com> |
drm/rockchip: dw-hdmi: Fix yuv422 display err
When switching from another color to yuv422, neither
encoder input color nor encoder output color is rgb.
CSC coeff will be incorrectly selected as
csc_
drm/rockchip: dw-hdmi: Fix yuv422 display err
When switching from another color to yuv422, neither
encoder input color nor encoder output color is rgb.
CSC coeff will be incorrectly selected as
csc_coeff_full_to_limited, which causes the display
turn to green. To solve this problem, choose
csc_coeff_full_to_limited only if the input and output
colors are both RGB.
Change-Id: If09f53fb2a5aa20359efb548b1a8b7da2c79310d
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
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