| 91e56900 | 11-Oct-2021 |
Lei Chen <lei.chen@rock-chips.com> |
drm/rockchip: hdmi: optionally force the output format to be RGB
Support HDMI can choose to output only RGB format
Signed-off-by: Lei Chen <lei.chen@rock-chips.com>
Change-Id: I32affcc6507aac9ced1f
drm/rockchip: hdmi: optionally force the output format to be RGB
Support HDMI can choose to output only RGB format
Signed-off-by: Lei Chen <lei.chen@rock-chips.com>
Change-Id: I32affcc6507aac9ced1fcae22411412d96bbd083
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| 72a8959e | 26-Sep-2021 |
Wyon Bi <bivvy.bi@rock-chips.com> |
video/drm: display: Add 'panel-timing' support
Change-Id: Id68b80728c6342473e7dde9b3222de2f5ae3f539
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com> |
| a5f116a3 | 24-Sep-2021 |
Damon Ding <damon.ding@rock-chips.com> |
drm/rockchip: vop: disable rb_swap by default
On RK3399 platform, R and B are swapped. If not set the default value,
the bmp will display abnormally when calling function
rockchip_vop_set_plane() ea
drm/rockchip: vop: disable rb_swap by default
On RK3399 platform, R and B are swapped. If not set the default value,
the bmp will display abnormally when calling function
rockchip_vop_set_plane() each time. Related codes were showed as below:
/*
* vop full need to treats rgb888 as bgr888 so we reverse the rb swap
* to workaround
*/
if (crtc_state->format == ROCKCHIP_FMT_RGB888 && VOP_MAJOR(vop_data->version) == 3)
crtc_state->rb_swap = !crtc_state->rb_swap;
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I450477017ae73c18dad806efec7a44ac3e49b094
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| 6b6b8331 | 07-Sep-2021 |
Sandy Huang <hjc@rock-chips.com> |
video/drm: add config for drm memory reserved
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I43e21a4fd57f93953af9cad9fd1cdca2f259eae3 |
| 963b371c | 08-Sep-2021 |
Sandy Huang <hjc@rock-chips.com> |
video/drm: rgb: add data bypass for rgb output
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I2ee4c9443e2e5146413b16f262b7beb232ed1314 |
| 9f415b59 | 15-Sep-2021 |
Wyon Bi <bivvy.bi@rock-chips.com> |
video/drm: analogix_dp: Fix display corruption in low temperature environment
Change-Id: I2b2bbbd93d0f7b315afefa14720acab5ccd31c6d
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com> |
| 7a589732 | 23-Aug-2021 |
Chris Zhong <zyw@rock-chips.com> |
video/drm: display: flush dcache for logo
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Change-Id: Id81527bf9425098a400b51c0c6cbb490dab4e150 |
| 6b898587 | 23-Aug-2021 |
Damon Ding <damon.ding@rock-chips.com> |
drm/rockchip: vop: support rk3288 MCU display
1.Add MCU display mode related register definition.
2.Change the control method of RS pin to GPIO control, because cannot
control RS pin through VOP_MCU
drm/rockchip: vop: support rk3288 MCU display
1.Add MCU display mode related register definition.
2.Change the control method of RS pin to GPIO control, because cannot
control RS pin through VOP_MCU_CTRL register.
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I59cbafc2c1d6350e9028c45d64f6897243414a33
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| 2eab0e46 | 20-Aug-2021 |
Algea Cao <algea.cao@rock-chips.com> |
drm/rockchip: hdmi: Check the color even if there is no baseparameter
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: Ife34b13f6dc6bcd5f478cd98794e2bc18fddcc12 |
| 89912f2d | 16-Jul-2021 |
Sandy Huang <hjc@rock-chips.com> |
drm/rockchip: vop2: move global init to vop2_preinit
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I7f4b5711fce58e5757d4c02ed0fc14d675e3bcf9 |
| dac93f83 | 18-Aug-2021 |
Chris Zhong <zyw@rock-chips.com> |
drm/rockchip: vop: correct the dclk_inv
The property pixelclk-active=1 in dts means dclk polarity is positive
edge, and set 0 to GRF or VOP register: lcdc_dclk_inv_sel. This bit
is reversed in uboot
drm/rockchip: vop: correct the dclk_inv
The property pixelclk-active=1 in dts means dclk polarity is positive
edge, and set 0 to GRF or VOP register: lcdc_dclk_inv_sel. This bit
is reversed in uboot, this patch corrects it.
In addition, the configuration of RV1126 has been added in this patch.
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Change-Id: I93af7e052fb18782a81e9c9b762a57411ef9283f
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| 2bfb6166 | 16-Jun-2021 |
Sandy Huang <hjc@rock-chips.com> |
video/drm: display: add force mode and default mode support
1.add 720p60 ad default mode when get edid failed
2.add the property at dts to enable some hot plug devices force output:
&route_hdmi
video/drm: display: add force mode and default mode support
1.add 720p60 ad default mode when get edid failed
2.add the property at dts to enable some hot plug devices force output:
&route_hdmi {
status = "okay";
"force-output";
force-bus-format = <MEDIA_BUS_FMT_GBR888_1X24>;
force_timing {
clock-frequency = <148500000>;
hactive = <1920>;
vactive = <1080>;
...
};
};
signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Ib7ec7f642bff528aaa910aade0b97f7b52a9610a
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| fc672cf1 | 05-Aug-2021 |
Algea Cao <algea.cao@rock-chips.com> |
drm/rockchip: hdmi: Support read hdmi information from aux block of baseparameter
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I9780ebe3115a9cfb77b7d42b2cb69b07798d10bb |
| ee008497 | 15-Jul-2021 |
Sandy Huang <hjc@rock-chips.com> |
drm/rockchip: vop2: add adjust cursor plane
when dts add cursor-win-id property and the id isn't matching with
plane_mask, we adjust to the correct cursor plane.
Signed-off-by: Sandy Huang <hjc@roc
drm/rockchip: vop2: add adjust cursor plane
when dts add cursor-win-id property and the id isn't matching with
plane_mask, we adjust to the correct cursor plane.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Ia03c05368847d0bd80843c374a4409e9b1962969
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| 34a72bf2 | 29-Jul-2021 |
Ding Ling Song <damon.ding@rock-chips.com> |
drm/rockchip: vop2: fix esmart0 register error.
The base register should be ESMART0_REGION0_CTRL.
Change-Id: I9c78725a766b8704e22450021f2c89ea8233c962
Signed-off-by: Damon Ding <damon.ding@rock-chi
drm/rockchip: vop2: fix esmart0 register error.
The base register should be ESMART0_REGION0_CTRL.
Change-Id: I9c78725a766b8704e22450021f2c89ea8233c962
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
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| 8b1fe597 | 25-Jun-2021 |
Sandy Huang <hjc@rock-chips.com> |
drm/rockchip: vop2: if dts assign plane mask no need to update this property
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I824ed7adc46901ffd06022d3662aed186bda4001 |
| 8895aec1 | 05-Jul-2021 |
Sandy Huang <hjc@rock-chips.com> |
drm/rockchip: vop2: add more debug info
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I91db54a5792df3794c85e72ce0a52c853a1c79a0 |
| fd72c52e | 05-Jul-2021 |
Guochun Huang <hero.huang@rock-chips.com> |
video/drm: combo_phy: modified phy difference description
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Change-Id: I3ff24bc2d6c5be1f19228364eac77bcdce8de947 |
| 01ccf957 | 24-Jun-2021 |
Guochun Huang <hero.huang@rock-chips.com> |
video/drm: combo_phy: Add support RK356X dsi
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Change-Id: Ia4567cb20592f8740b870e8845e122cb56991ba9 |
| e007876d | 25-Jun-2021 |
Sandy Huang <hjc@rock-chips.com> |
drm/rockchip: vop2: use the first unplug devices as main display
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I38b5349c538a06a50771ec5d413db1c0d462da95 |
| 65617e2f | 28-May-2021 |
Wyon Bi <bivvy.bi@rock-chips.com> |
video/drm: dsi: disable phy when power off
Change-Id: I9925ebecc557e4f0a615358010e4d71ad0e86b84
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com> |
| efb5a62d | 24-May-2021 |
Sandy Huang <hjc@rock-chips.com> |
drm/rockchip: vop2: rk3566 only support 3+3 policy
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Id67a6c4f1eb2680b3e328a7d011cdccfd6295e03 |
| 7a20be36 | 19-May-2021 |
Sandy Huang <hjc@rock-chips.com> |
video/drm: vop2: fix interlace fild pol config error
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I6491d18bbf2abe70226edc75ff7b49c2f7ac34ee |
| 62fc2a10 | 18-May-2021 |
Sandy Huang <hjc@rock-chips.com> |
drm/rockchip: vop2: force set rk3566 active_vp_num as two
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I2a39749993941cfd248445924b8770a8ed129db6 |
| 74bd8269 | 19-May-2021 |
Sandy Huang <hjc@rock-chips.com> |
drm/rockchip: vop2: sync vop2 limit from kernel
1. post scale must align as 2 pixel;
2. unsupport src_w % 16 == 1 when scale down.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I8a1e0a
drm/rockchip: vop2: sync vop2 limit from kernel
1. post scale must align as 2 pixel;
2. unsupport src_w % 16 == 1 when scale down.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I8a1e0a41933f6d7a1fb4f4224e6894df68692be7
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