| 957b4ee3 | 17-Aug-2017 |
Kever Yang <kever.yang@rock-chips.com> |
rockchip: rk322x: pinctrl: fix IO MASK error on sdcard pin
Fix the IOMUX setting for SDcard CMD pin at the same time.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Toms
rockchip: rk322x: pinctrl: fix IO MASK error on sdcard pin
Fix the IOMUX setting for SDcard CMD pin at the same time.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
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| e95b6312 | 25-Jul-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
rockchip: pinctrl: rk3368: add SPI support
To implement pinctrl support for the RK3368, we need to add the bit-definitions to configure the IOMUX and tie these into the pinctrl framework. This also
rockchip: pinctrl: rk3368: add SPI support
To implement pinctrl support for the RK3368, we need to add the bit-definitions to configure the IOMUX and tie these into the pinctrl framework. This also adds the mapping from the IRQ# back onto the periheral id for the SPI devices.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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| a49773d6 | 25-Jul-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
rockchip: pinctrl: rk3368: move IOMUX bit-definitions to pinctrl driver
There is no real reason to keep the bit-definitions for the IOMUX in the grf header file (which defines the register layout of
rockchip: pinctrl: rk3368: move IOMUX bit-definitions to pinctrl driver
There is no real reason to keep the bit-definitions for the IOMUX in the grf header file (which defines the register layout of the GRF block): these should only be used by our pinctrl driver (with the possible exception of early debug-init code in TPL/SPL).
This moves the relevant definitions from the grf_rk3368.h header into the pinctrl driver pinctrl_rk3368.c.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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| abcde475 | 14-Jul-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
rockchip: pinctrl: rk3368: add support for configuring the MMC pins
The RK3368 has two SD/MMC controllers that can be used from U-Boot both during SPL and for booting an OS from the full bootloader
rockchip: pinctrl: rk3368: add support for configuring the MMC pins
The RK3368 has two SD/MMC controllers that can be used from U-Boot both during SPL and for booting an OS from the full bootloader stage. While both are configured to (mostly) sensible settings from the BROM, additional configuration for the MMC controller is needed to configure it to 8bit mode.
This adds pinctrl support for the MMC controller.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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| 5282a3f1 | 14-Jul-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
rockchip: pinctrl: rk3368: add GMAC (RGMII only) support
To add GMAC (Gigabit Ethernet) support (limited to RGMII only at this point), we need support for additional pin-configuration. This commit
rockchip: pinctrl: rk3368: add GMAC (RGMII only) support
To add GMAC (Gigabit Ethernet) support (limited to RGMII only at this point), we need support for additional pin-configuration. This commit adds the pinctrl support for GMAC in RGMII mode: * adds a PERIPH_ID_GMAC and the mapping from IRQ number to PERIPH_ID * configures the RGMII pins
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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| 478e6f2e | 25-Jul-2017 |
Romain Perier <romain.perier@collabora.com> |
rockchip: rk3288: Add support for drive-strength in PINCTRL
Currently, drive-strenght to 12ma are described and supposed to be used on RK3288. However, the pinctrl driver for this SoC only handles m
rockchip: rk3288: Add support for drive-strength in PINCTRL
Currently, drive-strenght to 12ma are described and supposed to be used on RK3288. However, the pinctrl driver for this SoC only handles muxing and pull up/pull down via PU/PD control registers. So complex IPs like GMAC are working in normal ethernet 100mbps, but not at 1gbps typically.
This commit adds support for handling drive-strength of 12ma, when it's defined in the DT.
Signed-off-by: Romain Perier <romain.perier@collabora.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
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| 3641d346 | 17-Jul-2017 |
Romain Perier <romain.perier@collabora.com> |
rockchip: rk3288: Revert MAC_TXCLK in pinctrl for GMAC
This reverts TXCLK toggling that was accidently dropped while reworking commit 2454b719fb87 ("rockchip: rk3288: Add pinctrl support for the gma
rockchip: rk3288: Revert MAC_TXCLK in pinctrl for GMAC
This reverts TXCLK toggling that was accidently dropped while reworking commit 2454b719fb87 ("rockchip: rk3288: Add pinctrl support for the gmac ethernet interface"). So the TX clock is enabled and we can use GMAC_ROCKCHIP in 1Gbps when basic PINCTRL support is enabled (!PINTRL_FULL).
Fixes: 2454b719fb87 ("rockchip: rk3288: Add pinctrl support for the...") Signed-off-by: Romain Perier <romain.perier@collabora.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
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| 2454b719 | 26-Jun-2017 |
Sjoerd Simons <sjoerd.simons@collabora.co.uk> |
rockchip: rk3288: Add pinctrl support for the gmac ethernet interface
Add support for the gmac ethernet interface to pinctrl. This hardcodes the setup to match that of the firefly and Radxa Rock2 bo
rockchip: rk3288: Add pinctrl support for the gmac ethernet interface
Add support for the gmac ethernet interface to pinctrl. This hardcodes the setup to match that of the firefly and Radxa Rock2 boards, using the RGMII phy mode for gmac interface and GPIO4B0 as the phy reset GPIO.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Signed-off-by: Romain Perier <romain.perier@collabora.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
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| 077eb315 | 17-May-2017 |
Kever Yang <kever.yang@rock-chips.com> |
rockchip: pinctrl: rk3328: do not set io routing
In rk3328, some function pin may have more than one choice, and muxed with more than one IO, for example, the UART2 controller IO, TX and RX, have 3
rockchip: pinctrl: rk3328: do not set io routing
In rk3328, some function pin may have more than one choice, and muxed with more than one IO, for example, the UART2 controller IO, TX and RX, have 3 choice(setting in com_iomux): - M0 which mux with GPIO1A0/GPIO1A1 - M1 which mux with GPIO2A0/GPIO2A1 - usb2phy which mux with USB2.0 DP/DM pin.
We should not decide which group to use in pinctrl driver, for it may be different in different board, it should goes to board file, and the pinctrl file should setting correct iomux depends on the com_iomux value.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
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| 6f0c1237 | 17-May-2017 |
Kever Yang <kever.yang@rock-chips.com> |
rockchip: pinctrl: move rk3328 grf reg definition in header file
Move GRF register bit definition into GRF header file, remove 'GRF_' prefix and add 'GPIOmXn_' as prefix for bit meaning.
Signed-off
rockchip: pinctrl: move rk3328 grf reg definition in header file
Move GRF register bit definition into GRF header file, remove 'GRF_' prefix and add 'GPIOmXn_' as prefix for bit meaning.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
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