sunxi_nand_spl: Add support for sun4i and sun5i SoCs

Other then having a few less chip-select lines the nand controller
on sun4i, sun5i and sun7i is identical.

Note this patch also muxes GPC7 to th

sunxi_nand_spl: Add support for sun4i and sun5i SoCs

Other then having a few less chip-select lines the nand controller
on sun4i, sun5i and sun7i is identical.

Note this patch also muxes GPC7 to the NAND on sun7i where as before
it was not muxed this way. GPC7 is a standard NAND pin, so it should
always be muxed to the NAND when in use.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

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sunxi_nand_spl: Use kernel driver algorithm for determining ecc_mode / _off

Sync the code for figuring out the ecc_mode and ecc_offset with the linux
kernel v4.1. Keeping this in sync seems like a g

sunxi_nand_spl: Use kernel driver algorithm for determining ecc_mode / _off

Sync the code for figuring out the ecc_mode and ecc_offset with the linux
kernel v4.1. Keeping this in sync seems like a good idea in general, and
it fixes / adds support for ecc strengths of 56, 60 and 64 bits.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

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sunxi_nand_spl: Add proper cache flusing

We are using dma, so we should flush the cache before starting the dma,
and invalidate it once the dma is done.

Things are working without this by mostly lu

sunxi_nand_spl: Add proper cache flusing

We are using dma, so we should flush the cache before starting the dma,
and invalidate it once the dma is done.

Things are working without this by mostly luck, but lets not rely on that.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

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sunxi_nand_spl: Turn off clocks when we're done with the nand

Turn off the nand and dma clocks when we're done with the nand, this
puts the nand and dma controllers back into a clean state for when

sunxi_nand_spl: Turn off clocks when we're done with the nand

Turn off the nand and dma clocks when we're done with the nand, this
puts the nand and dma controllers back into a clean state for when the
kernel boots.

Without this the kernel will not boot properly when it is built with
dma-controller support.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

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sunxi_nand_spl: Use SYS_NAND_SELF_INIT and only do nand init when necessary

Use SYS_NAND_SELF_INIT and only setup the pinmux and clocks when we are
actually using the nand.

Signed-off-by: Hans de G

sunxi_nand_spl: Use SYS_NAND_SELF_INIT and only do nand init when necessary

Use SYS_NAND_SELF_INIT and only setup the pinmux and clocks when we are
actually using the nand.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

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sunxi_nand_spl: Do not bother writing the spare-area reg in syndrome mode

In syndrome mode we set the NFC_SEQ bit in the command register, so the
spare-area register is not used. Also the value curr

sunxi_nand_spl: Do not bother writing the spare-area reg in syndrome mode

In syndrome mode we set the NFC_SEQ bit in the command register, so the
spare-area register is not used. Also the value currently being written is
actual wrong, the ecc sits at "column + CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE"
not just CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE.

So the current code only serves to confuse the user -> remove it.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

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sunxi_nand_spl: We only need to reset the nand chip once

There is no need to reset the nand chip for every ecc-block read.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell

sunxi_nand_spl: We only need to reset the nand chip once

There is no need to reset the nand chip for every ecc-block read.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

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sunxi_nand_spl: Drop unnecessary temp buf

nand_spl_load_image() always gets called with either CONFIG_SYS_TEXT_BASE
or spl_image.load_addr as destination, both of which are properly aligened,
and ha

sunxi_nand_spl: Drop unnecessary temp buf

nand_spl_load_image() always gets called with either CONFIG_SYS_TEXT_BASE
or spl_image.load_addr as destination, both of which are properly aligened,
and have plenty of space for "overshooting" up to
CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE bytes, as we read in
CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE bytes chunks.

This saves CONFIG_NAND_SUNXI_SPL_ECC_PAGE_SIZE (typically 1k) in
SPL size, which is a lot on the total 24k we have.

Note this changes the dma destination from SRAM to DRAM, so this patch
updates the DDMA_DST_TYPE bits in the dma controller cfg0 reg accordingly.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>

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mtd: denali_spl: do not allocate page_buffer in .bss section

Since commit 2580a2a7e719 ("mtd: nand: Increase max sizes of OOB and
Page size"), three boards (ph1_ld4, ph1_pro4, ph1_sld8) fail to buil

mtd: denali_spl: do not allocate page_buffer in .bss section

Since commit 2580a2a7e719 ("mtd: nand: Increase max sizes of OOB and
Page size"), three boards (ph1_ld4, ph1_pro4, ph1_sld8) fail to build
with the following error message:
arm-linux-gnueabi-ld.bfd: SPL image plus BSS too big

They compile drivers/mtd/nand/denali_spl.c and it has a page_buffer
as static data:

static uint8_t page_buffer[NAND_MAX_PAGESIZE];

This buffer required 8KB in .bss section before that commit and now
it has been increased to 16KB. Given limited code/memory size for SPL,
it is not a good idea to allocate a page buffer statically. In the
first place, the load address 'dst' can be used as a page buffer.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

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mtd/nand/ubi: assortment of alignment fixes

Various U-Boot adoptions/extensions to MTD/NAND/UBI did not take buffer
alignment into account which led to failures of the following form:

ERROR: v7_dca

mtd/nand/ubi: assortment of alignment fixes

Various U-Boot adoptions/extensions to MTD/NAND/UBI did not take buffer
alignment into account which led to failures of the following form:

ERROR: v7_dcache_inval_range - start address is not aligned - 0x1f7f0108
ERROR: v7_dcache_inval_range - stop address is not aligned - 0x1f7f1108

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Scott Wood <scottwood@freescale.com>
[trini: Add __UBOOT__ hunk to lib/zlib/zutil.c due to malloc.h in common.h]
Signed-off-by: Tom Rini <trini@konsulko.com>

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mtd: nand: mxs invalidate dcache before DMA read

Follow linux dma flow:
Before DMA read, be sure to invalidate the cache over the address
range of DMA buffer to prevent cache coherency problems.
Aft

mtd: nand: mxs invalidate dcache before DMA read

Follow linux dma flow:
Before DMA read, be sure to invalidate the cache over the address
range of DMA buffer to prevent cache coherency problems.
After DMA read, invalidate dcache again.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Tim Harvey <tharvey@gateworks.com>

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mtd: nand: mxs support oobsize bigger than 512

If ecc chunk data size is 512 and oobsize is bigger than 512, there is
a chance that block_mark_bit_offset conflicts with bch ecc area.

The following

mtd: nand: mxs support oobsize bigger than 512

If ecc chunk data size is 512 and oobsize is bigger than 512, there is
a chance that block_mark_bit_offset conflicts with bch ecc area.

The following graph is modified from kernel gpmi-nand.c driver with
each data block 512 bytes. We can see that Block Mark conflicts with
ecc area from bch view. We can enlarge the ecc chunk size to avoid
this problem to those oobsize which is larger than 512.

| P |
|<----------------------------------------------------------------->|
| |
| (Block Mark) |
| P' | | | |
|<--------------------------------------------------->| D | | O'|
| |<--------->| |<->|
V V V V V
+---+--------------+-+--------------+-+--------------+-+----------+-+---+
| M | data |E| data |E| data |E| data |E| |
+---+--------------+-+--------------+-+--------------+-+----------+-+---+
^ ^
| O |
|<---------------->|

P : the page size for BCH module.
E : The ECC strength.
G : the length of Galois Field.
N : The chunk count of per page.
M : the metasize of per page.
C : the ecc chunk size, aka the "data" above.
P': the nand chip's page size.
O : the nand chip's oob size.
O': the free oob.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Tested-By: Tim Harvey <tharvey@gateworks.com>

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mtd: nand: Add mvebu (PXA / AXP / A38x) NAND device driver

Cloned from the Linux driver v4.2.0-rc2. Plus some patches from
Antoine Tenart enabling controller initialization and ONFI timing
support:

mtd: nand: Add mvebu (PXA / AXP / A38x) NAND device driver

Cloned from the Linux driver v4.2.0-rc2. Plus some patches from
Antoine Tenart enabling controller initialization and ONFI timing
support:

http://lists.infradead.org/pipermail/linux-mtd/2015-July/060197.html

Please note that this driver needs the Linux NAND subsystem sync to v4.1
from Scott to be applied:

https://www.mail-archive.com/u-boot@lists.denx.de/msg175762.html

Otherwise it will not compile.

Tested on the Marvell Armada XP DB-MV784MP-GP eval board.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Antoine Tenart <antoine.tenart@free-electrons.com>
Cc: Ezeguil Garcia <ezequiel.garcia@free-electrons.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Scott Wood <scottwood@freescale.com>

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nand: Sync with Linux v4.1

Update the NAND code to match Linux v4.1. The previous sync was
from Linux v3.15 in commit 4e67c57125290b25.

CONFIG_SYS_NAND_RESET_CNT is removed, as the upstream Linux

nand: Sync with Linux v4.1

Update the NAND code to match Linux v4.1. The previous sync was
from Linux v3.15 in commit 4e67c57125290b25.

CONFIG_SYS_NAND_RESET_CNT is removed, as the upstream Linux code now
has its own timeout. Plus, CONFIG_SYS_NAND_RESET_CNT was undocumented
and not selected by any board.

Signed-off-by: Scott Wood <scottwood@freescale.com>

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mtd: Introduce mtd_block_isreserved()

In addition to mtd_block_isbad(), which checks if a block is bad or
reserved, it's needed to check if a block is reserved only (but not
bad). This commit adds a

mtd: Introduce mtd_block_isreserved()

In addition to mtd_block_isbad(), which checks if a block is bad or
reserved, it's needed to check if a block is reserved only (but not
bad). This commit adds an MTD interface for it, in a similar fashion to
mtd_block_isbad().

While here, fix mtd_block_isbad() so the out-of-bounds checking is done
before the callback check.

Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Tested-by: Pekon Gupta <pekon@ti.com>
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
[scottwood: Cherry-picked from Linux 8471bb73ba10ed67]
Signed-off-by: Scott Wood <scottwood@freescale.com>

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nand: Remove __UBOOT__ ifdefs

I didn't approve the patch that added them. Get them out of the way
before doing a sync.

Signed-off-by: Scott Wood <scottwood@freescale.com>

nand: lpc32xx: add ECC layout for small page NAND

Incorporate ECC layout for small page NAND from legacy LPCLinux NXP BSP.
The code taken from the legacy patch is:
- lpc32xx SLC NAND driver (ECC lay

nand: lpc32xx: add ECC layout for small page NAND

Incorporate ECC layout for small page NAND from legacy LPCLinux NXP BSP.
The code taken from the legacy patch is:
- lpc32xx SLC NAND driver (ECC layout for small page)

This layout is matching the lpc32xx NAND SLC Linux Kernel driver.

Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>

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nand: lpc32xx: add hardware ECC support

Incorporate NAND SLC hardware ECC support from legacy LPCLinux NXP BSP.
The code taken from the legacy patch is:
- lpc32xx SLC NAND driver (hardware ECC suppo

nand: lpc32xx: add hardware ECC support

Incorporate NAND SLC hardware ECC support from legacy LPCLinux NXP BSP.
The code taken from the legacy patch is:
- lpc32xx SLC NAND driver (hardware ECC support)
- lpc3250 header file missing SLC NAND registers definition

The legacy driver was updated and clean-up as part of the integration with the existing NAND SLC driver.

Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Tested-by: Vladimir Zapolskiy <vz@mleia.com>

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tegra: nand: disable subpage writes

Disable subpage writes as we do not provide ecc->hwctl.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Scott Wood <scottwood@freescale.co

tegra: nand: disable subpage writes

Disable subpage writes as we do not provide ecc->hwctl.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>

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mtd/nand/tegra: alignment workaround

Integrate cache alignment bounce buffer to workaround issues as follows:

Loading file '/boot/zImage' to addr 0x01000000 with size 4499152 (0x0044a6d0)...
ERROR:

mtd/nand/tegra: alignment workaround

Integrate cache alignment bounce buffer to workaround issues as follows:

Loading file '/boot/zImage' to addr 0x01000000 with size 4499152 (0x0044a6d0)...
ERROR: v7_dcache_inval_range - start address is not aligned - 0x1f7f0108
ERROR: v7_dcache_inval_range - stop address is not aligned - 0x1f7f1108
Done
Kernel image @ 0x1000000 [ 0x000000 - 0x44a6d0 ]

Starting kernel ...

undefined instruction
pc : [<005ff03c>] lr : [<0000800c>]
sp : 0144b6e8 ip : 01000188 fp : 0144a6c8
r10: 00000000 r9 : 411fc090 r8 : 00000100
r7 : 00000cfb r6 : 0144a6d0 r5 : 00000000 r4 : 00008000
r3 : 0000000c r2 : 00000100 r1 : 00000cfb r0 : 00000000
Flags: nZCv IRQs off FIQs off Mode SVC_32
Resetting CPU ...

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>

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tegra: nand: fix read_byte required for proper onfi detection

Fix PIO read_byte() implementation not only used for the legacy READ ID
but also the PARAM command required for proper ONFI detection.

tegra: nand: fix read_byte required for proper onfi detection

Fix PIO read_byte() implementation not only used for the legacy READ ID
but also the PARAM command required for proper ONFI detection.

This fix is inspired by Lucas Stach's Linux Tegra NAND driver of late
(not mainline yet but getting there soon I hope).

I vaguely remember that those commands are special on 16-bit bus NAND
(e.g. always return 8-bit data regardless) and later Linux MTD fixed/
changed the way this is handled which in turn broke once U-Boot pulled
that in. Basically instead of doing PIO read regular DMA block read is
now used which this patch actually fixes.

Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Tom Warren <twarren@nvidia.com>

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nand: lpc32xx: add SLC NAND controller support

The change adds support of LPC32xx SLC NAND controller.

LPC32xx SoC has two different mutually exclusive NAND controllers to
communicate with single a

nand: lpc32xx: add SLC NAND controller support

The change adds support of LPC32xx SLC NAND controller.

LPC32xx SoC has two different mutually exclusive NAND controllers to
communicate with single and multiple layer chips.

This simple driver allows to specify NAND chip timings and defines
custom read_buf()/write_buf() operations, because access to 8-bit data
register must be 32-bit aligned.

Support of hardware ECC calculation is not implemented (data
correction is always done by software), since it requires a working
DMA engine.

The driver can be included to an SPL image.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Tested-by: Sylvain Lemieux <slemieux@tycoint.com>

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spl: nand: simple: replace readb() with chip specific read_buf()

Some NAND controllers define custom functions to read data out,
respect this in order to correctly support bad block handling in
simp

spl: nand: simple: replace readb() with chip specific read_buf()

Some NAND controllers define custom functions to read data out,
respect this in order to correctly support bad block handling in
simple SPL NAND framework.

NAND controller specific read_buf() is used even to read 1 byte in
case of connected 8-bit NAND device, it turns out that read_byte()
may become outdated.

Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Cc: Tom Rini <trini@konsulko.com>
Cc: Tom Warren <twarren@nvidia.com>
Acked-by: Scott Wood <scottwood@freescale.com>

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nand, atmel: remove udelay in spl_nand_erase_one()

remove unneeded udelay() in this function, as we use
the dev_ready pin.

Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Scott Wood <scottwood

nand, atmel: remove udelay in spl_nand_erase_one()

remove unneeded udelay() in this function, as we use
the dev_ready pin.

Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Scott Wood <scottwood@freescale.com>

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sunxi: nand: Add board configuration options

When SPL_NAND_SUNXI option is selected in config, set some configuration
options for sunxi NAND.

This commit also introduces the configurable options in

sunxi: nand: Add board configuration options

When SPL_NAND_SUNXI option is selected in config, set some configuration
options for sunxi NAND.

This commit also introduces the configurable options in Kconfig.

Signed-off-by: Peter Gielda <pgielda@antmicro.com>
Signed-off-by: Tomasz Gorochowik <tgorochowik@antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com>
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

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