UPSTREAM: mtd: nand: mxs_nand: add minimal ECC support

Add support for minimum ECC strength supported by the NAND chip.
This aligns with the behavior when using the fsl,use-minimum-ecc
device tree p

UPSTREAM: mtd: nand: mxs_nand: add minimal ECC support

Add support for minimum ECC strength supported by the NAND chip.
This aligns with the behavior when using the fsl,use-minimum-ecc
device tree property in Linux.

Change-Id: Id687fc1d9ce8c18ffb5ff387b08a486d220a34e8
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 984df7add1fe6e5a25854eae81f51940806456bc)

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UPSTREAM: mtd: nand: mxs_nand: report correct ECC parameters

Report correct ECC parameters back to the stack. Do not report
bytes as we have it not immeaditly available and the Linux version
also do

UPSTREAM: mtd: nand: mxs_nand: report correct ECC parameters

Report correct ECC parameters back to the stack. Do not report
bytes as we have it not immeaditly available and the Linux version
also does not report it. It seems to have no aversive effect.

Change-Id: Iacb4717a287b40bc301c31b7ab5b8c93be3c209b
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 5c69dd0730ff6bcad16e86fd93bf7a914d988a22)

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UPSTREAM: mtd: nand: mxs_nand: use structure for BCH geometry

Calculate BCH geometry at start and store the information in
a structure. This avoids recalculation on every page access
and allows to c

UPSTREAM: mtd: nand: mxs_nand: use structure for BCH geometry

Calculate BCH geometry at start and store the information in
a structure. This avoids recalculation on every page access
and allows to calculate ECC relevant information in one place.
This patch does not change ECC layout or driver behavior in
any way.

The patch aligns the driver somewhat with the Linux GPMI NAND
driver which drives the same IP.

Change-Id: Ia89d8c67ed0016e1f0da29d84ac90d477b16385e
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 28897e8d21f8e197e259a91c693de09cd81f2d5a)

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UPSTREAM: mtd: nand: mxs_nand: allow to enable BBT support

Add config option which allows to enable on flash bad block table
support. This has the same effect as when using the device tree
property

UPSTREAM: mtd: nand: mxs_nand: allow to enable BBT support

Add config option which allows to enable on flash bad block table
support. This has the same effect as when using the device tree
property "nand-on-flash-bbt" in Linux.

Change-Id: If72080027de5d703ba3609e9fc5f6a791bcc7b01
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit dc0b69fa9f97df90cbcabf16a51d7eb88f26cd2d)

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UPSTREAM: mtd: nand: mxs_nand: use self init

Instead of completing initialization via scan_bbt callback use
NAND self init to initialize the GPMI (MXS) NAND controller.

Suggested-by: Scott Wood <os

UPSTREAM: mtd: nand: mxs_nand: use self init

Instead of completing initialization via scan_bbt callback use
NAND self init to initialize the GPMI (MXS) NAND controller.

Suggested-by: Scott Wood <oss@buserror.net>
Change-Id: I27a3a5c32edd3f5c27dd7385875656cc1c6ece62
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 5346c31e305a37d39f535cc0d5ae87d8b7e81230)

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UPSTREAM: mtd: nand: mxs_nand: introduce SPL specific init

In preparation to convert the driver to use NAND self init
provide a new minimal init for SPL builds. As a side effect
this also reduces si

UPSTREAM: mtd: nand: mxs_nand: introduce SPL specific init

In preparation to convert the driver to use NAND self init
provide a new minimal init for SPL builds. As a side effect
this also reduces size of SPL by about 4KiB.

Change-Id: I8450871ce30793a3526057cc5be322ebb0ae8d14
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 9345943b2b5ea890cb479770c3c802cf851ed3e6)

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UPSTREAM: nand: zynq: Send address cycles as per onfi parameter page

Send address cycles as per value read from onfi parameter
page for Read and write commands instead of using a
hard coded value. T

UPSTREAM: nand: zynq: Send address cycles as per onfi parameter page

Send address cycles as per value read from onfi parameter
page for Read and write commands instead of using a
hard coded value. This may vary for different parts and
hence use it from onfi parameter page value.

Change-Id: I16512bb8cb560148af32c7746d23539a6676c466
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 9fdde6c4bbb6840dd175f0c29dfcc791fc0c1d2a)

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UPSTREAM: nand: zynq: Add support for 16-bit buswidth

This patch adds support for 16-bit buswidth by determining
the bus width based on mio configuration.

Change-Id: I821bb2d5fe8bc8e5173d590ae408f1

UPSTREAM: nand: zynq: Add support for 16-bit buswidth

This patch adds support for 16-bit buswidth by determining
the bus width based on mio configuration.

Change-Id: I821bb2d5fe8bc8e5173d590ae408f16d767a083f
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 9ca8388059de8f10e035fbdcaa418ec3caeb0599)

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UPSTREAM: mtd: nand: tegra: convert to driver model and live tree

The Tegra NAND driver recently got broken by ongoing driver model resp.
live tree migration work:

NAND: Could not decode nand-flas

UPSTREAM: mtd: nand: tegra: convert to driver model and live tree

The Tegra NAND driver recently got broken by ongoing driver model resp.
live tree migration work:

NAND: Could not decode nand-flash in device tree
Tegra NAND init failed
0 MiB

A patch for NAND uclass support was proposed about a year ago:
https://patchwork.ozlabs.org/patch/722282/

It was not merged and I do not see on-going work for this.

This commit just provides a driver model probe hook to retrieve further
configuration from the live device tree. As there is no NAND ulass as of
yet (ab)using UCLASS_MTD. Once UCLASS_NAND is supported, it would be
possible to migrate to it.

Change-Id: Idc7dc3440cc6158d61bf41150bde9c5010e30486
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 4b11a6296aab84b628434cdbdd15697fab8a3a93)

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UPSTREAM: mtd: nand: fsl_ifc: Fix nand waitfunc return value

As per the IFC hardware manual, Most significant byte in nand_fsr
register is the outcome of NAND READ STATUS command.

So status value n

UPSTREAM: mtd: nand: fsl_ifc: Fix nand waitfunc return value

As per the IFC hardware manual, Most significant byte in nand_fsr
register is the outcome of NAND READ STATUS command.

So status value need to be shifted as per the nand framework
requirement.

Change-Id: I0cb0278f83f3ea6d3768660dcb3e169e47fcbdd1
Signed-off-by: Jagdish Gediya <jagdish.gediya@nxp.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit e8c669a3e6ec9b33aea55e957024f97300b99c1c)

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UPSTREAM: mtd: nand: fsl_ifc: Fix eccstat array overflow for IFC ver >= 2.0.0

Number of ECC status registers i.e. (ECCSTATx) has been increased in
IFC version 2.0.0 due to increase in SRAM size. Thi

UPSTREAM: mtd: nand: fsl_ifc: Fix eccstat array overflow for IFC ver >= 2.0.0

Number of ECC status registers i.e. (ECCSTATx) has been increased in
IFC version 2.0.0 due to increase in SRAM size. This is causing
eccstat array to over flow.

So, replace eccstat array with u32 variable to make it fail-safe and
independent of number of ECC status registers or SRAM size.

Change-Id: I00699a36b57beed284afeccf44001ee4373d9bb6
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Jagdish Gediya <jagdish.gediya@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit f195fad178979020b226671cafec9f9592860174)

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UPSTREAM: nand: zynq: Cleanup initialization

CONFIG_NAND_ZYNQ selects CONFIG_SYS_NAND_SELF_INIT, so the
driver doesn't have to play any ifdef game.

Also, we can mark zynq_nand_init() as static and

UPSTREAM: nand: zynq: Cleanup initialization

CONFIG_NAND_ZYNQ selects CONFIG_SYS_NAND_SELF_INIT, so the
driver doesn't have to play any ifdef game.

Also, we can mark zynq_nand_init() as static and get rid
of the mach-specific nand.h header.

This is really a revert of:
"mtd: zynq: nand: Move board_nand_init() function to board.c"
(sha1: 310995d9f91ae56082b49be06fe8c3d01424f8f6)

Change-Id: I3d435d645c911c88bdf1d25600896141cd37d54e
Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 41b7d7f241221ab9f0888f47f31226cfa74a971a)

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UPSTREAM: nand: zynq: Fix driver initialization

This driver is currently broken, refusing to initialize properly.

The reason is that get_nand_dev_by_index() was being called before
nand_register(),

UPSTREAM: nand: zynq: Fix driver initialization

This driver is currently broken, refusing to initialize properly.

The reason is that get_nand_dev_by_index() was being called before
nand_register(), thus returning a pointer into uninitialized memory.
In other words, the struct mtd_info used by the driver is total junk.

Fix it by getting the correct struct mtd_info, via nand_to_mtd()
on the driver's struct nand_chip.

Tested on a custom board, where the CPU is halted without this patch.

Change-Id: I372eca6bfe6e6ca53612d8f2d8bcc5cdfe620222
Signed-off-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 07c5cbbd1e6573e169687da873db37503a1f8b60)

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UPSTREAM: nand: arasan_nfc: Fixed NAND write issue

In commit 2453c695185f ("arm64: zynqmp: nand: Fixed NAND erase issue for
size 1GiB or more"), ARASAN_NAND_MEM_ADDR1_PAGE_MASK macro changed
to 0xFF

UPSTREAM: nand: arasan_nfc: Fixed NAND write issue

In commit 2453c695185f ("arm64: zynqmp: nand: Fixed NAND erase issue for
size 1GiB or more"), ARASAN_NAND_MEM_ADDR1_PAGE_MASK macro changed
to 0xFFFF and the same macro is used in nand write and so that getting
nand write error.
This patch reverted this macro to the 0xFFFF0000 and used
ARASAN_NAND_MEM_ADDR1_COL_MASK in the nand erase function
which is equal to 0xFFFF.

Change-Id: Iae3ff9baf6bb1c05512c8432c346fafbb1bf6225
Signed-off-by: Vipul Kumar <vipulk@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 6fbbe2d8f671920948a0b1882c6884cfdd0cbe67)

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UPSTREAM: sunxi: move the NAND parameters to Kconfig

Move the NAND parameters from defconfig files to Kconfig for SUNXI
architecture only. Fort now only the CHIP pro is migrated.

It would have been

UPSTREAM: sunxi: move the NAND parameters to Kconfig

Move the NAND parameters from defconfig files to Kconfig for SUNXI
architecture only. Fort now only the CHIP pro is migrated.

It would have been better to convert this defconfig entry to Kconfig for
all supported machines/architectures but it has been abandoned due to a
fairly high amount of errors reported by the moveconfig.py tool. This is
due to defines quite often being multiplications of values/other defines
not correctly handled.

Change-Id: I9010719934b53180d2af15e45acabc45dd39d039
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 748b5b34d3d0e67923cac5f8606b7a209e063df6)

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UPSTREAM: sunxi: make NAND_SUNXI use ARCH_SUNXI as default in Kconfig

Remove NAND_SUNXI from the CHIP pro defconfig to be automatically
selected depending on the state of ARCH_SUNXI.

Change-Id: I49

UPSTREAM: sunxi: make NAND_SUNXI use ARCH_SUNXI as default in Kconfig

Remove NAND_SUNXI from the CHIP pro defconfig to be automatically
selected depending on the state of ARCH_SUNXI.

Change-Id: I49bec5ad57be81004a5836adeebd40b5fabe55e4
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit b56052f4ca40d0d8b29fb7bd3be4c104618e4fc8)

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UPSTREAM: sunxi: automatically select SPL_NAND_SUPPORT in Kconfig

Make SUNXI_NAND select SPL_NAND_SUPPORT in Kconfig, this limit the
number of entries to add in defconfig files when adding NAND supp

UPSTREAM: sunxi: automatically select SPL_NAND_SUPPORT in Kconfig

Make SUNXI_NAND select SPL_NAND_SUPPORT in Kconfig, this limit the
number of entries to add in defconfig files when adding NAND support.

For now, the only board using it is the CHIP pro.

Change-Id: Ia308aa9a877a06912571510d18a00e3aaaff0403
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 6d094d535c121637775b5108f1e78e426017f757)

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UPSTREAM: sunxi: allow NAND support to be compiled for sun8i platforms

Add some clocks/PLL definitions as well as the dependency on MACH_SUN8I
in Kconfig.

Change-Id: I8fb0229aa90d5b837c3f2a735dc1b1

UPSTREAM: sunxi: allow NAND support to be compiled for sun8i platforms

Add some clocks/PLL definitions as well as the dependency on MACH_SUN8I
in Kconfig.

Change-Id: I8fb0229aa90d5b837c3f2a735dc1b169dca37b06
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 663e8a9b54ccbc9b939e4e3696a84fdf2f5a43fc)

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UPSTREAM: spl: nand: sunxi: use PIO instead of DMA

SPL support was first written to support only the earlier generations of
Allwinner SoCs, and was only really enabled on the A13 / GR8. However,
tho

UPSTREAM: spl: nand: sunxi: use PIO instead of DMA

SPL support was first written to support only the earlier generations of
Allwinner SoCs, and was only really enabled on the A13 / GR8. However,
those old SoCs had a DMA engine that has been replaced since the A31 by
another DMA controller that is no longer compatible.

Since the code directly uses that DMA controller, it cannot operate
properly on the later SoCs, while the NAND controller has not changed.

There's two paths forward, the first one would have been to add support
for that DMA controller too, the second to just remove the DMA usage
entirely and rely on PIO.

The later has been chosen because CPU overload at this stage is not an
issue and it makes the driver more generic, and easier to understand.

Change-Id: I6c237da0e67d520568903d77c84103c98730ccc2
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 6ddbb1e936c78cdef1e7395039fa7020c5c75326)

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UPSTREAM: spl: nand: sunxi: declare the ecc_bytes array globally

Move the ecc_bytes array out of nand_max_ecc_strength() for future use
by nand_read_page().

Change-Id: I0dc537a460183bc3352adfbe2163

UPSTREAM: spl: nand: sunxi: declare the ecc_bytes array globally

Move the ecc_bytes array out of nand_max_ecc_strength() for future use
by nand_read_page().

Change-Id: I0dc537a460183bc3352adfbe2163eab84d3cdbeb
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 7440bd7885da984dc20e2e8c8a0b167911e9dce1)

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UPSTREAM: spl: nand: sunxi: make the reset column helper more generic

Prepare the future use of an helper to move the data pointer (the
column) of the NAND chip by renaming nand_reset_column() to
na

UPSTREAM: spl: nand: sunxi: make the reset column helper more generic

Prepare the future use of an helper to move the data pointer (the
column) of the NAND chip by renaming nand_reset_column() to
nand_change_column(). Resetting the column is just a matter of giving 0
as argument.

Change-Id: Ie311136768de7f7d6e92eb56afe1af9b39d4d93d
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 22f0aa0528a48cb9eb72abb065071e47c4215af9)

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UPSTREAM: spl: nand: sunxi: ensure enough time has passed after changing the column

When changing the column, the ONFI specification states that a minimum
time of tCCS (Change Column Setup time) mus

UPSTREAM: spl: nand: sunxi: ensure enough time has passed after changing the column

When changing the column, the ONFI specification states that a minimum
time of tCCS (Change Column Setup time) must elapse between the last
address cycle is asserted on the bus and the first data cycle is
clocked. An usual value for average NANDs is 500 nanoseconds. Round it
up to 1 microsecond to be safe.

Change-Id: If9f02bf0861da520e9c7e6288e41986cbb8fbe0e
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 4dac80a5e991dd3b5b99910d7927edfdf4c99bb3)

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UPSTREAM: spl: nand: sunxi: create an helper to handle command execution

Executing a command is matter of always doing the following sequence:
* Waiting for the FIFO to be empty so we can fill it

UPSTREAM: spl: nand: sunxi: create an helper to handle command execution

Executing a command is matter of always doing the following sequence:
* Waiting for the FIFO to be empty so we can fill it with the new
command.
* Clearing the status register.
* Writing the command in the FIFO.
* Waiting for the command to finish.

Add a nand_exec_cmd() helper to handle this instead of repeating the
logic through the various functions.

Change-Id: If33cb5d361838472d12580c97a5ddaed80f08945
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit a084cb6664e0de40f33da1c8ec6de816a9852f6d)

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UPSTREAM: spl: nand: sunxi: add missing status clear

It is best practice to always clear the status register before executing
a command to be sure that the status read afterwards is relevant.

Chang

UPSTREAM: spl: nand: sunxi: add missing status clear

It is best practice to always clear the status register before executing
a command to be sure that the status read afterwards is relevant.

Change-Id: I70a36f514d8f820521541ed0b7473dc31f9c5824
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 781e70cff12916ae6698cc77a22e0ce687f39e3b)

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UPSTREAM: spl: nand: sunxi: introduce the nand_wait_cmd_fifo_empty() helper

One bit in the control registers indicates if the NAND controller is
ready to receive a new command. Otherwise, the comman

UPSTREAM: spl: nand: sunxi: introduce the nand_wait_cmd_fifo_empty() helper

One bit in the control registers indicates if the NAND controller is
ready to receive a new command. Otherwise, the command FIFO is full and
we should wait for this bit to flip. It then states that the last
command has been processed and the FIFO is now free to welcome another
command.

Add this sanity check before starting any new command.

Change-Id: I55a93fc0b3f889c40cf0e4fbb40eeeb3e46df17b
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Acked-by: Boris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
(cherry picked from commit 60fb17913354757d015ade2b5457675a0506903a)

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