| ec7aa8fd | 21-Feb-2017 |
Yung-Ching LIN <yungching0725@gmail.com> |
board: ge: bx50v3: apply the proper register setting to fix the voltage peak issue
Apply the proper setting for the reserved bits in SetDes Test and System Mode Control register to avoid the voltage
board: ge: bx50v3: apply the proper register setting to fix the voltage peak issue
Apply the proper setting for the reserved bits in SetDes Test and System Mode Control register to avoid the voltage peak issue while we do the IEEE PHY comformance test
Signed-off-by: Ken Lin <yungching0725@gmail.com> Reviewed-by: Stefano Babic <sbabic@denx.de> Acked-by: Ian Ray <ian.ray@ge.com>
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| 8d293f49 | 12-Apr-2016 |
Akshay Bhat <akshay.bhat@timesys.com> |
board: ge: bx50v3: Fix to meet LVDS display power on timing
On a reset/reboot, the display power needs to be off for atleast 500ms before turning it back on. So add a delay to the boot process to me
board: ge: bx50v3: Fix to meet LVDS display power on timing
On a reset/reboot, the display power needs to be off for atleast 500ms before turning it back on. So add a delay to the boot process to meet the display timing requirement.
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com> Cc: Stefano Babic <sbabic@denx.de>
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| 494d43ec | 12-Apr-2016 |
Akshay Bhat <akshay.bhat@timesys.com> |
board: ge: bx50v3: Setup LDB_DI_CLK source
To generate accurate pixel clocks required by the displays we need to set the ldb_di_clk source on bx50v3 to PLL3 and b850v3 to PLL5. Since PLL5 is disable
board: ge: bx50v3: Setup LDB_DI_CLK source
To generate accurate pixel clocks required by the displays we need to set the ldb_di_clk source on bx50v3 to PLL3 and b850v3 to PLL5. Since PLL5 is disabled on reset, we need to enable PLL5.
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com> Cc: Stefano Babic <sbabic@denx.de>
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