| cb69e4de | 10-Feb-2009 |
Kumar Gala <galak@kernel.crashing.org> |
85xx: print boot header info to distinquish 36-bit addr map on MPC8572 DS
Added some info that is printed out when we boot to distiquish if we built MPC8572DS_config vs MPC8572DS_36BIT_config since
85xx: print boot header info to distinquish 36-bit addr map on MPC8572 DS
Added some info that is printed out when we boot to distiquish if we built MPC8572DS_config vs MPC8572DS_36BIT_config since they have different address maps.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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| feede8b0 | 06-Dec-2008 |
Andy Fleming <afleming@freescale.com> |
Fixup SGMII PHY ids in the device tree
The device tree's PHY addresses need to be fixed up if we're using the SGMII Riser Card.
The 8572, 8536, and 8544 DS boards were modified to call this functio
Fixup SGMII PHY ids in the device tree
The device tree's PHY addresses need to be fixed up if we're using the SGMII Riser Card.
The 8572, 8536, and 8544 DS boards were modified to call this function.
Code idea taken from Liu Yu <yu.liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
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| b6730512 | 10-Feb-2009 |
Kumar Gala <galak@kernel.crashing.org> |
85xx: Fix bug in device tree setup in 36-bit physical confg
In the 36-bit physical config for MPC8572DS when need the start address of memory and it size to be kept in phys_*_t instead of a ulong si
85xx: Fix bug in device tree setup in 36-bit physical confg
In the 36-bit physical config for MPC8572DS when need the start address of memory and it size to be kept in phys_*_t instead of a ulong since we support >4G of memory in the config and ulong cant represent that. Otherwise we end up seeing the memory node in the device tree reporting back we have memory starting @ 0 and of size 0.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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| b5f65dfa | 13-Jan-2009 |
Haiying Wang <Haiying.Wang@freescale.com> |
Some changes of TLB entry setting for MPC8572DS
- Move the TLB entry of PIXIS_BASE from TLB0 to TLB1[8], because in CAMP mode, all the TLB0 entries will be invalidated after cpu1 brings up kernel, t
Some changes of TLB entry setting for MPC8572DS
- Move the TLB entry of PIXIS_BASE from TLB0 to TLB1[8], because in CAMP mode, all the TLB0 entries will be invalidated after cpu1 brings up kernel, thus cpu0 can not access PIXIS_BASE anymore (any access will cause DataTLBError exception)
- Set CONFIG_SYS_DDR_TLB_START to 9 for MPC8572DS board.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
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