| 38dba0c2 | 17-Dec-2010 |
Becky Bruce <beckyb@kernel.crashing.org> |
mpc85xx boards: initdram() cleanup/bugfix
Correct initdram to use phys_size_t to represent the size of dram; instead of changing this all over the place, and correcting all the other random errors I
mpc85xx boards: initdram() cleanup/bugfix
Correct initdram to use phys_size_t to represent the size of dram; instead of changing this all over the place, and correcting all the other random errors I've noticed, create a common initdram that is used by all non-corenet 85xx parts. Most of the initdram() functions were identical, with 2 common differences:
1) DDR tlbs for the fixed_sdram case were set up in initdram() on some boards, and were part of the tlb_table on others. I have changed them all over to the initdram() method - we shouldn't be accessing dram before this point so they don't need to be done sooner, and this seems cleaner.
2) Parts that require the DDR11 erratum workaround had different implementations - I have adopted the version from the Freescale errata document. It also looks like some of the versions were buggy, and, depending on timing, could have resulted in the DDR controller being disabled. This seems bad.
The xpedite boards had a common/fsl_8xxx_ddr.c; with this change only the 517 board uses this so I have moved the ddr code into that board's directory in xpedite517x.c
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Tested-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
show more ...
|
| b6bde930 | 29-Sep-2010 |
Haiying Wang <Haiying.Wang@freescale.com> |
mpc8569mds: fix some ddr settings
Enable half drive strength, set RTT to 60Ohm and set write leveling override.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <g
mpc8569mds: fix some ddr settings
Enable half drive strength, set RTT to 60Ohm and set write leveling override.
Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
show more ...
|
| 3fca8037 | 15-Oct-2009 |
Anton Vorontsov <avorontsov@ru.mvista.com> |
mpc85xx: Configure QE USB for MPC8569E-MDS boards
Setup QE pin multiplexing for USB function, configure needed BCSRs and add some fdt fixups.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.co
mpc85xx: Configure QE USB for MPC8569E-MDS boards
Setup QE pin multiplexing for USB function, configure needed BCSRs and add some fdt fixups.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
show more ...
|
| 14809b6c | 15-Oct-2009 |
Anton Vorontsov <avorontsov@ru.mvista.com> |
mpc85xx: Configure QE UART for MPC8569E-MDS boards
To make QE UART usable by Linux we should setup pin multiplexing and turn UCC2 Ethernet node into UCC2 QE UART node.
Also, QE UART is mutually exc
mpc85xx: Configure QE UART for MPC8569E-MDS boards
To make QE UART usable by Linux we should setup pin multiplexing and turn UCC2 Ethernet node into UCC2 QE UART node.
Also, QE UART is mutually exclusive with UART0, so we can't enable it if eSDHC is in 4-bits mode on pilot boards, or if it's a prototype board with eSDHC in 1- or 4-bits mode.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
show more ...
|
| 70d665b1 | 15-Oct-2009 |
Anton Vorontsov <avorontsov@ru.mvista.com> |
mpc85xx: Setup QE pinmux for SPI Flash on MPC8569E-MDS boards
SPI Flash (M25P40) is connected to the SPI1 bus, we need a few qe_iop entries to actually enable SPI1 on these boards.
Signed-off-by: A
mpc85xx: Setup QE pinmux for SPI Flash on MPC8569E-MDS boards
SPI Flash (M25P40) is connected to the SPI1 bus, we need a few qe_iop entries to actually enable SPI1 on these boards.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
show more ...
|
| 65dec3b4 | 15-Oct-2009 |
Anton Vorontsov <avorontsov@ru.mvista.com> |
mpc85xx: Setup SRIO memory region LAW for MPC8569E-MDS boards
This patch sets memory window for Serial RapidIO on MPC8569E-MDS boards.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Sign
mpc85xx: Setup SRIO memory region LAW for MPC8569E-MDS boards
This patch sets memory window for Serial RapidIO on MPC8569E-MDS boards.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
show more ...
|
| a29155e1 | 15-Oct-2009 |
Anton Vorontsov <avorontsov@ru.mvista.com> |
mpc85xx: Add eLBC NAND support for MPC8569E-MDS boards
Simply add some defines, and adjust TLBe setup to include some space for eLBC NAND.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
mpc85xx: Add eLBC NAND support for MPC8569E-MDS boards
Simply add some defines, and adjust TLBe setup to include some space for eLBC NAND.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
show more ...
|