| 10d569ea | 11-May-2016 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Fix up PIRQ routing table checksum earlier
PIRQ routing table checksum is fixed up in copy_pirq_routing_table(),
which is fine if we only write the configuration table once. But with
the SeaBIO
x86: Fix up PIRQ routing table checksum earlier
PIRQ routing table checksum is fixed up in copy_pirq_routing_table(),
which is fine if we only write the configuration table once. But with
the SeaBIOS case, when we write the table for the second time, the
checksum will be fixed up to zero per the checksum algorithm, which
is caused by the checksum field not being zero before fix up, since
the checksum has already been calculated in the first run.
To fix this, move the checksum fixup to create_pirq_routing_table(),
so that copy_pirq_routing_table() only does what its function name
suggests: copy the table to somewhere else.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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| 34865a65 | 23-May-2016 |
Miao Yan <yanmiaobest@gmail.com> |
x86: qemu: fix ACPI Kconfig options
CONFIG_GENENRATE_ACPI_TABLE controls the generation of ACPI table which
uses U-Boot's built-in methods and CONFIG_QEMU_ACPI_TABLE controls whether
to load ACPI ta
x86: qemu: fix ACPI Kconfig options
CONFIG_GENENRATE_ACPI_TABLE controls the generation of ACPI table which
uses U-Boot's built-in methods and CONFIG_QEMU_ACPI_TABLE controls whether
to load ACPI table from QEMU's fw_cfg interface.
But with commit "697ec431469ce0a4c2fc2c02d8685d907491af84 x86: qemu: Drop
our own ACPI implementation", there is only one way to support ACPI table
for QEMU targets which is the fw_cfg interface. Having two Kconfig options
for this purpose is not necessary any more, so this patch consolidates
the two.
Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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| 7e6343ef | 07-May-2016 |
Bin Meng <bmeng.cn@gmail.com> |
x86: acpi: Clean up table header revisions
The comment of initializing table header revision says:
/* ACPI 1.0/2.0: 1, ACPI 3.0: 2, ACPI 4.0: 3 */
which might mislead it may increase per ACPI
x86: acpi: Clean up table header revisions
The comment of initializing table header revision says:
/* ACPI 1.0/2.0: 1, ACPI 3.0: 2, ACPI 4.0: 3 */
which might mislead it may increase per ACPI spec revision.
However this is not the case. It's actually a fixed number
as defined in ACPI spec, and in the laest ACPI spec 6.1,
some table header revisions are still 1. Clean these up.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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| 25e133ec | 07-May-2016 |
Bin Meng <bmeng.cn@gmail.com> |
x86: acpi: Align FACS table to a 64 byte boundary
Per ACPI spec, the FACS table address must be aligned to a 64 byte
boundary (Windows checks this, but Linux does not).
Signed-off-by: Bin Meng <bme
x86: acpi: Align FACS table to a 64 byte boundary
Per ACPI spec, the FACS table address must be aligned to a 64 byte
boundary (Windows checks this, but Linux does not).
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
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| 7e79a6bc | 07-May-2016 |
Bin Meng <bmeng.cn@gmail.com> |
x86: acpi: Use u32 in table write routines
Use u32 instead of unsigned long in the table write routines, as
other routines do.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass
x86: acpi: Use u32 in table write routines
Use u32 instead of unsigned long in the table write routines, as
other routines do.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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| ab5efd57 | 07-May-2016 |
Bin Meng <bmeng.cn@gmail.com> |
x86: acpi: Adjust order in acpi_table.c
Rearrange the routine order a little bit, to follow the order
in which ACPI table is defined in acpi_table.h.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
R
x86: acpi: Adjust order in acpi_table.c
Rearrange the routine order a little bit, to follow the order
in which ACPI table is defined in acpi_table.h.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
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| dfbb18bc | 07-May-2016 |
Bin Meng <bmeng.cn@gmail.com> |
x86: acpi: Change fill_header()
Rename fill_header() to acpi_fill_header() for consistency.
Change its signature to remove the 'length' parameter and
make it a public API.
Also remove the unnecessa
x86: acpi: Change fill_header()
Rename fill_header() to acpi_fill_header() for consistency.
Change its signature to remove the 'length' parameter and
make it a public API.
Also remove the unnecessary include files, and improve the
AmlCode[] comment a little bit.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
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| cea91319 | 07-May-2016 |
Bin Meng <bmeng.cn@gmail.com> |
x86: acpi: Remove acpi_create_ssdt_generator()
This acpi_create_ssdt_generator() currently does nothing.
Remove this for now.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese
x86: acpi: Remove acpi_create_ssdt_generator()
This acpi_create_ssdt_generator() currently does nothing.
Remove this for now.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
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| 8a8c0352 | 07-May-2016 |
Bin Meng <bmeng.cn@gmail.com> |
x86: acpi: Various changes to acpi_table.h
- Use "U-BOOT" and "U-BOOTBL" for the OEM ID and OEM table ID.
- Do not typedef acpi_header_t, instead use struct acpi_table_hader.
- Use a shorter name as
x86: acpi: Various changes to acpi_table.h
- Use "U-BOOT" and "U-BOOTBL" for the OEM ID and OEM table ID.
- Do not typedef acpi_header_t, instead use struct acpi_table_hader.
- Use a shorter name aslc_id and aslc-revision.
- Change MCFG base address to use 32-bit value pairs (_l and _h).
- Apply ACPI_APIC_ prefix to MADT APIC type macros and make
their names to be more readable.
- Apply __packed to struct acpi_madt_irqoverride and struct
acpi_madt_lapic_nmi tables, as they are not naturally aligned
by the compiler which leads to wrong sizeof(struct).
- Rename model to res1 as it is reserved after ACPI spec 1.0.
- Apply ACPI_ prefix to the PM profile macros and change them
to enum.
- Add ospm_flags to FACS structure which is defined since ACPI 4.0.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
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| dca4d1a2 | 07-May-2016 |
Bin Meng <bmeng.cn@gmail.com> |
x86: acpi: Fix compiler warnings in write_acpi_tables()
Fix the following two build warnings in function 'write_acpi_tables':
warning: format '%lx' expects argument of type 'long unsigned int',
x86: acpi: Fix compiler warnings in write_acpi_tables()
Fix the following two build warnings in function 'write_acpi_tables':
warning: format '%lx' expects argument of type 'long unsigned int',
but argument 2 has type 'u32' [-Wformat=]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
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| 7ac99be6 | 12-Mar-2016 |
Simon Glass <sjg@chromium.org> |
x86: Add an ICH6 pin configuration driver
Add a driver which sets up the pin configuration on x86 devices with an ICH6
(or later) Platform Controller Hub.
The driver is not in the pinctrl uclass du
x86: Add an ICH6 pin configuration driver
Add a driver which sets up the pin configuration on x86 devices with an ICH6
(or later) Platform Controller Hub.
The driver is not in the pinctrl uclass due to some oddities of the way x86
devices work:
- The GPIO controller is not present in I/O space until it is set up
- This is done by writing a register in the PCH
- The PCH has a driver which itself uses PCI, another driver
- The pinctrl uclass requires that a pinctrl device be available before any
other device can be probed
It would be possible to work around the limitations by:
- Hard-coding the GPIO address rather than reading it from the PCH
- Using special x86 PCI access to set the GPIO address in the PCH
However it is not clear that this is better, since the pin configuration
driver does not actually provide normal pin configuration services - it
simply sets up all the pins statically when probed. While this remains the
case, it seems better to use a syscon uclass instead. This can be probed
whenever it is needed, without any limitations.
Also add an 'invert' property to support inverting the input.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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| 3cf23719 | 29-Feb-2016 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Support booting SeaBIOS
SeaBIOS is an open source implementation of a 16-bit x86 BIOS.
It can run in an emulator or natively on x86 hardware with the
use of coreboot. With SeaBIOS's help, we ca
x86: Support booting SeaBIOS
SeaBIOS is an open source implementation of a 16-bit x86 BIOS.
It can run in an emulator or natively on x86 hardware with the
use of coreboot. With SeaBIOS's help, we can boot some OSes
that require 16-bit BIOS services like Windows/DOS.
As U-Boot, we have to manually create a table where SeaBIOS gets
system information (eg: E820) from. The table unfortunately has
to follow the coreboot table format as SeaBIOS currently supports
booting as a coreboot payload.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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| 26f9a9b7 | 28-Feb-2016 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Implement functions for writing coreboot table
To prepare generating coreboot table from U-Boot, implement functions
to handle the writing.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewe
x86: Implement functions for writing coreboot table
To prepare generating coreboot table from U-Boot, implement functions
to handle the writing.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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| ff94c219 | 28-Feb-2016 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Support writing configuration tables in high area
For those secondary bootloaders like SeaBIOS who want to live in
the F segment, which conflicts the configuration table address,
now we allow w
x86: Support writing configuration tables in high area
For those secondary bootloaders like SeaBIOS who want to live in
the F segment, which conflicts the configuration table address,
now we allow write_tables() to write the configuration tables in
high area (malloc'ed memory).
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
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| ef4d0a52 | 28-Feb-2016 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Simplify codes in write_tables()
Given all table write routines have the same signature, we can
simplify the codes by using a function table.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Revie
x86: Simplify codes in write_tables()
Given all table write routines have the same signature, we can
simplify the codes by using a function table.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
show more ...
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