| d0b6f247 | 17-Apr-2013 |
Simon Glass <sjg@chromium.org> |
x86: Re-enable PCAT timer 2 for beeping
While we don't want PCAT timers for timing, we want timer 2 so that we can still make a beep. Re-purpose the PCAT driver for this, and enable it in coreboot.
x86: Re-enable PCAT timer 2 for beeping
While we don't want PCAT timers for timing, we want timer 2 so that we can still make a beep. Re-purpose the PCAT driver for this, and enable it in coreboot.
Signed-off-by: Simon Glass <sjg@chromium.org>
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| f9083bbe | 17-Apr-2013 |
Simon Glass <sjg@chromium.org> |
x86: Remove ISR timer
This is no longer used since we prefer the more accurate TSC timer, so remove the dead code.
Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Graeme Russ <graeme.russ@g
x86: Remove ISR timer
This is no longer used since we prefer the more accurate TSC timer, so remove the dead code.
Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Graeme Russ <graeme.russ@gmail.com>
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| e761ecdb | 17-Apr-2013 |
Simon Glass <sjg@chromium.org> |
x86: Add TSC timer
This timer runs at a rate that can be calculated, well over 100MHz. It is ideal for accurate timing and does not need interrupt servicing.
Tidy up some old broken and unneeded im
x86: Add TSC timer
This timer runs at a rate that can be calculated, well over 100MHz. It is ideal for accurate timing and does not need interrupt servicing.
Tidy up some old broken and unneeded implementations at the same time.
To provide a consistent view of boot time, we use the same time base as coreboot. Use the base timestamp supplied by coreboot as U-Boot's base time.
Signed-off-by: Simon Glass <sjg@chromium.org>base Signed-off-by: Simon Glass <sjg@chromium.org>
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