| 45ccec8f | 23-Oct-2014 |
Masahiro Yamada <yamada.m@jp.panasonic.com> |
kconfig: move CONFIG_USE_PRIVATE_LIBGCC to Kconfig
The private libgcc is supported only on ARM, MIPS, PowerPC, SH, x86. Those architectures should "select" HAVE_PRIVATE_LIBGCC and CONFIG_USE_PRIVATE
kconfig: move CONFIG_USE_PRIVATE_LIBGCC to Kconfig
The private libgcc is supported only on ARM, MIPS, PowerPC, SH, x86. Those architectures should "select" HAVE_PRIVATE_LIBGCC and CONFIG_USE_PRIVATE_LIBGCC should depend on it.
Currently, this option is enabled on Tegra boards and x86 architecture. Move the definition from header files to Kconfig.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org> Cc: Stephen Warren <swarren@nvidia.com> Cc: Tom Warren <twarren@nvidia.com>
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| 0d0ba59c | 20-Oct-2014 |
Simon Glass <sjg@chromium.org> |
x86: Rewrite bootm.c to make it similar to ARM
The x86 bootm code is quite special, and geared to zimage. Adjust it to support device tree and make it more like the ARM code, with separate bootm sta
x86: Rewrite bootm.c to make it similar to ARM
The x86 bootm code is quite special, and geared to zimage. Adjust it to support device tree and make it more like the ARM code, with separate bootm stages and functions for each stage.
Create a function announce_and_cleanup() to handle printing the "Starting kernel ..." message and put it in bootm so it is in one place and can be used by any loading code. Also move the board_final_cleanup() function into bootm.
Signed-off-by: Simon Glass <sjg@chromium.org>
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| d0b6f247 | 17-Apr-2013 |
Simon Glass <sjg@chromium.org> |
x86: Re-enable PCAT timer 2 for beeping
While we don't want PCAT timers for timing, we want timer 2 so that we can still make a beep. Re-purpose the PCAT driver for this, and enable it in coreboot.
x86: Re-enable PCAT timer 2 for beeping
While we don't want PCAT timers for timing, we want timer 2 so that we can still make a beep. Re-purpose the PCAT driver for this, and enable it in coreboot.
Signed-off-by: Simon Glass <sjg@chromium.org>
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| e761ecdb | 17-Apr-2013 |
Simon Glass <sjg@chromium.org> |
x86: Add TSC timer
This timer runs at a rate that can be calculated, well over 100MHz. It is ideal for accurate timing and does not need interrupt servicing.
Tidy up some old broken and unneeded im
x86: Add TSC timer
This timer runs at a rate that can be calculated, well over 100MHz. It is ideal for accurate timing and does not need interrupt servicing.
Tidy up some old broken and unneeded implementations at the same time.
To provide a consistent view of boot time, we use the same time base as coreboot. Use the base timestamp supplied by coreboot as U-Boot's base time.
Signed-off-by: Simon Glass <sjg@chromium.org>base Signed-off-by: Simon Glass <sjg@chromium.org>
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| fa790fa0 | 17-Apr-2013 |
Simon Glass <sjg@chromium.org> |
x86: Remove legacy board init code
Since we use CONFIG_SYS_GENERIC_BOARD on x86, we don't need this anymore.
Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Graeme Russ <graeme.russ@gmail.c
x86: Remove legacy board init code
Since we use CONFIG_SYS_GENERIC_BOARD on x86, we don't need this anymore.
Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Graeme Russ <graeme.russ@gmail.com>
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