| 29756d44 | 17-Apr-2013 |
Simon Glass <sjg@chromium.org> |
x86: Remove old broken timer implementation
Tidy up some old broken and unneeded implementations. These are not used
by coreboot or anything else now.
Signed-off-by: Simon Glass <sjg@chromium.org>
x86: Remove old broken timer implementation
Tidy up some old broken and unneeded implementations. These are not used
by coreboot or anything else now.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Reviewed-by: Michael Spang <spang@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Acked-by: Graeme Russ <graeme.russ@gmail.com>
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| e761ecdb | 17-Apr-2013 |
Simon Glass <sjg@chromium.org> |
x86: Add TSC timer
This timer runs at a rate that can be calculated, well over 100MHz. It is
ideal for accurate timing and does not need interrupt servicing.
Tidy up some old broken and unneeded im
x86: Add TSC timer
This timer runs at a rate that can be calculated, well over 100MHz. It is
ideal for accurate timing and does not need interrupt servicing.
Tidy up some old broken and unneeded implementations at the same time.
To provide a consistent view of boot time, we use the same time
base as coreboot. Use the base timestamp supplied by coreboot
as U-Boot's base time.
Signed-off-by: Simon Glass <sjg@chromium.org>base
Signed-off-by: Simon Glass <sjg@chromium.org>
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| 7949703a | 17-Apr-2013 |
Simon Glass <sjg@chromium.org> |
x86: Rationalise kernel booting logic and bootstage
The 'Starting linux' message appears twice in the code, but both call
through the same place. Unify these and add calls to bootstage to
mark the o
x86: Rationalise kernel booting logic and bootstage
The 'Starting linux' message appears twice in the code, but both call
through the same place. Unify these and add calls to bootstage to
mark the occasion.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Michael Spang <spang@chromium.org>
Acked-by: Graeme Russ <graeme.russ@gmail.com>
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| f82d15ea | 28-Feb-2013 |
Simon Glass <sjg@chromium.org> |
x86: Rearrange the output input to remove BSS
At present BSS data is including in the image, which wastes binary space.
Remove it by rearranging the sections so that BSS is last.
Signed-off-by: Sim
x86: Rearrange the output input to remove BSS
At present BSS data is including in the image, which wastes binary space.
Remove it by rearranging the sections so that BSS is last.
Signed-off-by: Simon Glass <sjg@chromium.org>
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| c9466317 | 03-Nov-2012 |
Stefan Reinauer <reinauer@chromium.org> |
x86: drop unused code in coreboot.c
The function setup_pcat_compatibility() is weak and implemented as empty
function in board.c hence we don't have to override that with another
empty function.
mo
x86: drop unused code in coreboot.c
The function setup_pcat_compatibility() is weak and implemented as empty
function in board.c hence we don't have to override that with another
empty function.
monitor_flash_len is unused, drop it.
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
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| 2b9d2252 | 03-Nov-2012 |
Stefan Reinauer <reinauer@chromium.org> |
x86: Remove coreboot_ from file name
... because that information is already "encoded" in the directory name.
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@
x86: Remove coreboot_ from file name
... because that information is already "encoded" in the directory name.
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
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| 1350f1cc | 03-Nov-2012 |
Vadim Bendebury <vbendeb@chromium.org> |
x86: Provide a way to throttle port80 accesses
Some systems (like Google Link device) provide the ability to keep a
history of the target CPU port80 accesses, which is extremely handy
for debugging.
x86: Provide a way to throttle port80 accesses
Some systems (like Google Link device) provide the ability to keep a
history of the target CPU port80 accesses, which is extremely handy
for debugging. The problem is that the EC handling port 80 access is
orders of magnitude slower than the AP. This causes random loss of
trace data.
This change allows to throttle port 80 accesses such that in case the
AP is trying to post faster than the EC can handle, a delay is
introduced to make sure that the post rate is throttled. Experiments
have shown that on Link the delay should be at least 350,000 of tsc
clocks.
Throttling is not being enabled by default: to enable it one would
have to set MIN_PORT80_KCLOCKS_DELAY to something like 400 and rebuild
the u-boot image. With upcoming EC code optimizations this number
could be decreased (new new value should be established
experimentally).
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
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| 7c71034d | 03-Dec-2012 |
Vadim Bendebury <vbendeb@chromium.org> |
x86: Provide tick counter and frequency reference for Intel core architecture
Some u-boot modules rely on availability of get_ticks() and
get_tbclk() functions, reporting a free running clock and it
x86: Provide tick counter and frequency reference for Intel core architecture
Some u-boot modules rely on availability of get_ticks() and
get_tbclk() functions, reporting a free running clock and its
frequency respectively. Traditionally these functions return number
and frequency of timer interrupts.
Intel's core architecture processors however are known to run the
rdtsc instruction at a constant rate of the so called 'Max Non Turbo
ratio' times the external clock frequency which is 100MHz. This is
just as good for the timer tick functions in question.
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
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| b83058cd | 03-Nov-2012 |
Duncan Laurie <dlaurie@chromium.org> |
x86: Issue SMI to finalize Coreboot in final stage
This will write magic value to APMC command port which
will trigger an SMI and cause coreboot to lock down
the ME, chipset, and CPU.
Signed-off-by
x86: Issue SMI to finalize Coreboot in final stage
This will write magic value to APMC command port which
will trigger an SMI and cause coreboot to lock down
the ME, chipset, and CPU.
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
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