x86: ivybridge: Use reset_cpu()

Now that reset_cpu() functions correctly, use it instead of directly
accessing the port.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.c

x86: ivybridge: Use reset_cpu()

Now that reset_cpu() functions correctly, use it instead of directly
accessing the port.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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x86: Implement reset_cpu() correctly for modern CPUs

The existing code is pretty ancient and is unreliable on modern hardware.
Generally it will hang.

We can use port 0xcf9 to initiate reset on mor

x86: Implement reset_cpu() correctly for modern CPUs

The existing code is pretty ancient and is unreliable on modern hardware.
Generally it will hang.

We can use port 0xcf9 to initiate reset on more modern hardware (say in the
last 10 years). Update the reset_cpu() function to do this, and add a new
'full reset' function to perform a full power cycle.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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x86: link: Add PCH driver to support SPI Flash

U-Boot on coreboot does not have a driver for the PCH so cannot see the
SPI peripheral now that it has moved inside the PCH. Add a simple driver so
tha

x86: link: Add PCH driver to support SPI Flash

U-Boot on coreboot does not have a driver for the PCH so cannot see the
SPI peripheral now that it has moved inside the PCH. Add a simple driver so
that SPI flash works again.

Signed-off-by: Simon Glass <sjg@chromium.org>

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x86: quark: Turn on legacy segments decode

By default the legacy segments (A0000h-B0000h, E0000h-F0000h)
do not decode to system RAM. Turn on the decode so that we can
write configuration tables in

x86: quark: Turn on legacy segments decode

By default the legacy segments (A0000h-B0000h, E0000h-F0000h)
do not decode to system RAM. Turn on the decode so that we can
write configuration tables in the F segment.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

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x86: queensbay: Implement PIRQ routing

Implement Intel Queensbay platform-specific PIRQ routing support.
The chipset PIRQ routing setup is called in the arch_misc_init().

Signed-off-by: Bin Meng <b

x86: queensbay: Implement PIRQ routing

Implement Intel Queensbay platform-specific PIRQ routing support.
The chipset PIRQ routing setup is called in the arch_misc_init().

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

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x86: Write configuration tables in last_stage_init()

We can write the configuration table in last_stage_init() for all x86
boards, but not with coreboot since coreboot already has them.

Signed-off-

x86: Write configuration tables in last_stage_init()

We can write the configuration table in last_stage_init() for all x86
boards, but not with coreboot since coreboot already has them.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

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x86: Add a function to assign IRQ numbers to PCI device

Add a function to assign an IRQ number to PCI device's interrupt
line register in its configuration space, so that the PCI device
can have its

x86: Add a function to assign IRQ numbers to PCI device

Add a function to assign an IRQ number to PCI device's interrupt
line register in its configuration space, so that the PCI device
can have its interrupt working under PIC mode after OS boots up.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

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x86: queensbay: Avoid using PCH prefix

The prefix PCH was taken from ivybridge port. However Queensbay
platform official document does not mention PCH. It is composed
of TunnelCreek processor and To

x86: queensbay: Avoid using PCH prefix

The prefix PCH was taken from ivybridge port. However Queensbay
platform official document does not mention PCH. It is composed
of TunnelCreek processor and Topcliff IOH chipset. For accuracy,
avoid using PCH prefix in the macro.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

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Kconfig: Move CONFIG_BOOTSTAGE to Kconfig

Move CONFIG_BOOT_STAGE and its associated options to Kconfig. Adjust
existing users and code.

Signed-off-by: Simon Glass <sjg@chromium.org>

x86: chromebook_link: dts: Add PCH and LPC devices

The PCH (Platform Controller Hub) is on the PCI bus, so show it as such.
The LPC (Low Pin Count) and SPI bus are inside the PCH, so put these in th

x86: chromebook_link: dts: Add PCH and LPC devices

The PCH (Platform Controller Hub) is on the PCI bus, so show it as such.
The LPC (Low Pin Count) and SPI bus are inside the PCH, so put these in the
right place also.

Rename the compatible strings to be more descriptive since this board is the
only user. Once we are using driver model fully on x86, these will be
dropped.

Signed-off-by: Simon Glass <sjg@chromium.org>

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dm: x86: Add a uclass for a Platform Controller Hub

Add a simple uclass for this chip which is often found in x86 systems
where the CPU is a separate device.

The device can have children, so make i

dm: x86: Add a uclass for a Platform Controller Hub

Add a simple uclass for this chip which is often found in x86 systems
where the CPU is a separate device.

The device can have children, so make it scan the device tree for these.

Signed-off-by: Simon Glass <sjg@chromium.org>

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dm: x86: spi: Convert ICH SPI driver to driver model

Convert this driver over to use driver model. Since all x86 platforms use
it, move x86 to use driver model for SPI and SPI flash. Adjust all depe

dm: x86: spi: Convert ICH SPI driver to driver model

Convert this driver over to use driver model. Since all x86 platforms use
it, move x86 to use driver model for SPI and SPI flash. Adjust all dependent
code and remove the old x86 spi_init() function.

Note that this does not make full use of the new PCI uclass as yet. We still
scan the bus looking for the device. It should move to finding its details
in the device tree.

Signed-off-by: Simon Glass <sjg@chromium.org>

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dm: x86: pci: Convert chromebook_link to use driver model for pci

Move chromebook_link over to driver model for PCI.

This involves:
- adding a uclass for platform controller hub
- removing most of

dm: x86: pci: Convert chromebook_link to use driver model for pci

Move chromebook_link over to driver model for PCI.

This involves:
- adding a uclass for platform controller hub
- removing most of the existing PCI driver
- adjusting how CPU init works to use driver model instead
- rename the lpc compatible string (it will be removed later)

This does not really take advantage of driver model fully, but it does work.
Furture work will improve the code structure to remove many of the explicit
calls to init the board.

Signed-off-by: Simon Glass <sjg@chromium.org>

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dm: x86: pci: Convert coreboot to use driver model for pci

Move coreboot-x86 over to driver model for PCI.

Signed-off-by: Simon Glass <sjg@chromium.org>

dm: x86: pci: Add a PCI driver for driver model

Add a simple x86 PCI driver which uses standard functions provided by the
architecture.

Signed-off-by: Simon Glass <sjg@chromium.org>

x86: Split up arch_cpu_init()

At present we do more in this function than we should. Split out the
post-driver-model part into a separate function.

Signed-off-by: Simon Glass <sjg@chromium.org>
Rev

x86: Split up arch_cpu_init()

At present we do more in this function than we should. Split out the
post-driver-model part into a separate function.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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x86: Add a x86_ prefix to the x86-specific PCI functions

These functions currently use a generic name, but they are for x86 only.
This may introduce confusion and prevents U-Boot from using these na

x86: Add a x86_ prefix to the x86-specific PCI functions

These functions currently use a generic name, but they are for x86 only.
This may introduce confusion and prevents U-Boot from using these names
more widely.

In fact it should be possible to remove these at some point and use
generic functions, but for now, rename them.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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x86: Support machines with >4GB of RAM

Some systems have more than 4GB of RAM. U-Boot can only place things below
4GB so any memory above that should not be used. Ignore any such memory so
that the

x86: Support machines with >4GB of RAM

Some systems have more than 4GB of RAM. U-Boot can only place things below
4GB so any memory above that should not be used. Ignore any such memory so
that the memory size will not exceed the maximum.

This prevents gd->ram_size exceeding 4GB which causes problems for PCI
devices which use DMA.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>

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x86: quark: Enable on-chip ethernet controllers

Intel Quark SoC integrates two 10/100 ethernet controllers which can
be connected to an external RMII PHY. The MAC IP is from Designware.
Enable this

x86: quark: Enable on-chip ethernet controllers

Intel Quark SoC integrates two 10/100 ethernet controllers which can
be connected to an external RMII PHY. The MAC IP is from Designware.
Enable this support with the existing U-Boot Designware MAC driver
so that the ethernet port on Intel Galileo board can be used.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

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arch/x86/cpu/quark/mrc.c: Switch to U_BOOT_DATE / U_BOOT_TIME

Using __DATE__ and __TIME__ results in an error due to -Werror=date-time
with gcc-4.9 (__DATE__ / __TIME__ might prevent reproducible bu

arch/x86/cpu/quark/mrc.c: Switch to U_BOOT_DATE / U_BOOT_TIME

Using __DATE__ and __TIME__ results in an error due to -Werror=date-time
with gcc-4.9 (__DATE__ / __TIME__ might prevent reproducible builds) so
switch these over to U_BOOT_DATE / U_BOOT_TIME

Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@ti.com>
Acked-by: Simon Glass <sjg@chromium.org>

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x86: quark: MRC codes clean up

This patch cleans up the quark MRC codes coding style by:
- Remove BIT0/1../31 defines from mrc_util.h
- Create names for the documented BITs and use them
- For undocu

x86: quark: MRC codes clean up

This patch cleans up the quark MRC codes coding style by:
- Remove BIT0/1../31 defines from mrc_util.h
- Create names for the documented BITs and use them
- For undocumented single BITs, use (1 << n) directly
- For undocumented ORed BITs, use the hex number directly
- Remove redundancy parenthesis all over the codes
- Replace to use lower case hex numbers

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

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remove unnecessary version.h includes

Various files are needlessly rebuilt every time due to the version and
build time changing. As version.h is not actually needed, remove the
include.

Signed-off

remove unnecessary version.h includes

Various files are needlessly rebuilt every time due to the version and
build time changing. As version.h is not actually needed, remove the
include.

Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Minkyu Kang <mk7.kang@samsung.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Tom Warren <twarren@nvidia.com>
Cc: Michal Simek <monstr@monstr.eu>
Cc: Macpaul Lin <macpaul@andestech.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: York Sun <yorksun@freescale.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Simon Glass <sjg@chromium.org>
Cc: Philippe Reynes <tremyfr@yahoo.fr>
Cc: Eric Jarrige <eric.jarrige@armadeus.org>
Cc: "David Müller" <d.mueller@elsoft.ch>
Cc: Phil Edworthy <phil.edworthy@renesas.com>
Cc: Robert Baldyga <r.baldyga@samsung.com>
Cc: Torsten Koschorrek <koschorrek@synertronixx.de>
Cc: Anatolij Gustschin <agust@denx.de>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Łukasz Majewski <l.majewski@samsung.com>

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x86: Add SD/MMC support to quark/galileo

Intel Galileo board has a microSD slot which is routed from Quark SoC
SDIO controller. Enable SD/MMC support so that we can use an SD card.

Signed-off-by: B

x86: Add SD/MMC support to quark/galileo

Intel Galileo board has a microSD slot which is routed from Quark SoC
SDIO controller. Enable SD/MMC support so that we can use an SD card.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

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x86: Add SPI support to quark/galileo

The Quark SoC contains a legacy SPI controller in the legacy bridge
which is ICH7 compatible. Like Tunnel Creek and BayTrail, the BIOS
control register offset i

x86: Add SPI support to quark/galileo

The Quark SoC contains a legacy SPI controller in the legacy bridge
which is ICH7 compatible. Like Tunnel Creek and BayTrail, the BIOS
control register offset in the ICH SPI driver is wrong for the Quark
SoC too, unprotect_spi_flash() is added to enable the flash write.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

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x86: quark: Initialize non-standard BARs

Quark SoC has some non-standard BARs (excluding PCI standard BARs)
which need be initialized with suggested values. This includes GPIO,
WDT, RCBA, PCIe ECAM

x86: quark: Initialize non-standard BARs

Quark SoC has some non-standard BARs (excluding PCI standard BARs)
which need be initialized with suggested values. This includes GPIO,
WDT, RCBA, PCIe ECAM and some ACPI register block base addresses.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

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