| a8ebf283 | 22-Jul-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: qemu: Enable writing MP table
Enable writing MP table for QEMU boads (i440fx and q35).
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org> |
| c77b8912 | 22-Jul-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Allow cpu-x86 driver to be probed for UP
Currently cpu-x86 driver is probed only for SMP. We add the same
support for UP when there is only one cpu node in the deive tree.
Signed-off-by: Bin M
x86: Allow cpu-x86 driver to be probed for UP
Currently cpu-x86 driver is probed only for SMP. We add the same
support for UP when there is only one cpu node in the deive tree.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
show more ...
|
| e7cd070d | 22-Jul-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: qemu: Enable I/O APIC chip select on PIIX3
The PIIX3 chipset does not integrate an I/O APIC, instead it supports
connecting to an external I/O APIC which needs to be enabled manually.
Signed-o
x86: qemu: Enable I/O APIC chip select on PIIX3
The PIIX3 chipset does not integrate an I/O APIC, instead it supports
connecting to an external I/O APIC which needs to be enabled manually.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
show more ...
|
| a2771943 | 18-Jul-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Convert to use driver model pci on queensbay/crownbay
Move to driver model pci for Intel queensbay/crownbay.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> |
| 6fc0e8a1 | 15-Jul-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: pci: Do not assign irq 0 to pci device
IRQ 0 is reserved and should not be assigned to pci device.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org> |
| 31a2dc69 | 15-Jul-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: pci: Assign pci irqs to all functions
We need walk through all functions within a PCI device and assign
their IRQs accordingly.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Gla
x86: pci: Assign pci irqs to all functions
We need walk through all functions within a PCI device and assign
their IRQs accordingly.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
show more ...
|
| 93f8a311 | 15-Jul-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Enable DM RTC support for all x86 boards
Add a RTC node in the device tree to enable DM RTC support.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
(Squa
x86: Enable DM RTC support for all x86 boards
Add a RTC node in the device tree to enable DM RTC support.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
(Squashed in 'x86: Fix RTC build error on ivybridge')
show more ...
|
| 8ba25eec | 15-Jul-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Change pci option rom area MTRR setting to cacheable
Turn on cache on the pci option rom area to improve the performance.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sj
x86: Change pci option rom area MTRR setting to cacheable
Turn on cache on the pci option rom area to improve the performance.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
show more ...
|
| 3ccd49ca | 10-Jul-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Simplify architecture defined exception handling in irq_llsr()
Instead of using switch..case for architecture defined exceptions,
simply unify the handling by printing a message of exception na
x86: Simplify architecture defined exception handling in irq_llsr()
Instead of using switch..case for architecture defined exceptions,
simply unify the handling by printing a message of exception name,
followed by registers dump then halt the CPU.
With this unification, it also fixes the wrong exception numbers
for #MF/#AC/#MC/#XM which should be 16/17/18/19 not 15/16/17/18.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
show more ...
|
| 013cf483 | 10-Jul-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Display correct CS/EIP/EFLAGS when there is an error code
Some exceptions cause an error code to be saved on the current stack
after the EIP value. We should extract CS/EIP/EFLAGS from differen
x86: Display correct CS/EIP/EFLAGS when there is an error code
Some exceptions cause an error code to be saved on the current stack
after the EIP value. We should extract CS/EIP/EFLAGS from different
position on the stack based on the exception number.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
show more ...
|
| b0c8f4a7 | 17-Jul-2015 |
Masahiro Yamada <yamada.masahiro@socionext.com> |
Kill unneeded #include <linux/kconfig.h>
Because the top-level Makefile forces all the source files
to include include/linux/kconfig.h (see the UBOOTINCLUDE define),
these includes are redundant.
B
Kill unneeded #include <linux/kconfig.h>
Because the top-level Makefile forces all the source files
to include include/linux/kconfig.h (see the UBOOTINCLUDE define),
these includes are redundant.
By the way, there are exceptions for the statement above; host
programs. In fact, host tools in U-Boot depend on a particular
board configuration, although I think they should not. So, some
files still include <linux/config.h> to work around build errors
on host tools.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Simon Glass <sjg@chromium.org>
show more ...
|
| b9da5086 | 04-Jul-2015 |
Simon Glass <sjg@chromium.org> |
dm: x86: baytrail: Correct PCI region 3 when driver model is used
Commit afbbd413a fixed this for non-driver-model. Make sure that the driver
model code handles this also.
Signed-off-by: Simon Glas
dm: x86: baytrail: Correct PCI region 3 when driver model is used
Commit afbbd413a fixed this for non-driver-model. Make sure that the driver
model code handles this also.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
show more ...
|
| b71f9dca | 04-Jul-2015 |
Simon Glass <sjg@chromium.org> |
dm: x86: minnowmax: Move PCI to use driver model
Adjust minnowmax to use driver model for PCI. This requires adding a device
tree node to specify the ranges, removing the board-specific PCI code and
dm: x86: minnowmax: Move PCI to use driver model
Adjust minnowmax to use driver model for PCI. This requires adding a device
tree node to specify the ranges, removing the board-specific PCI code and
ensuring that the host bridge is configured.
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
show more ...
|
| 945cae79 | 04-Jul-2015 |
Simon Glass <sjg@chromium.org> |
x86: pci: Tidy up the generic x86 PCI driver
This driver should use the x86 PCI configuration functions. Also adjust its
compatible string to something generic (i.e. without a vendor name).
Signed-
x86: pci: Tidy up the generic x86 PCI driver
This driver should use the x86 PCI configuration functions. Also adjust its
compatible string to something generic (i.e. without a vendor name).
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
show more ...
|
| 92587b36 | 06-Jul-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: queensbay: Change CPU_ADDR_BITS to 32
Per CPUID:80000008h result, the maximum physical address bits of
TunnelCreek processor is 32 instead of default 36. This will fix
the incorrect decoding of
x86: queensbay: Change CPU_ADDR_BITS to 32
Per CPUID:80000008h result, the maximum physical address bits of
TunnelCreek processor is 32 instead of default 36. This will fix
the incorrect decoding of MTRR range mask.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
show more ...
|
| 43dd22f5 | 06-Jul-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Setup fixed range MTRRs for legacy regions
We should setup fixed range MTRRs for some legacy regions like VGA
RAM and PCI ROM areas as uncacheable. Note FSP may setup these to
other cache setti
x86: Setup fixed range MTRRs for legacy regions
We should setup fixed range MTRRs for some legacy regions like VGA
RAM and PCI ROM areas as uncacheable. Note FSP may setup these to
other cache settings, but we can override this in x86_cpu_init_f().
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
show more ...
|
| cdb6babe | 23-Jun-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: queensbay: Change PCIe root ports' interrupt routing
So far interrupt routing works pretty well for any on-chip devices
on Intel Crown Bay. When inserting any PCIe card to any PCIe slot,
Linux
x86: queensbay: Change PCIe root ports' interrupt routing
So far interrupt routing works pretty well for any on-chip devices
on Intel Crown Bay. When inserting any PCIe card to any PCIe slot,
Linux kernel is smart enough to do interrupt swizzling and figure
out device's irq using its parent bridge's interrupt routing info
all the way up to its root port. In U-Boot all PCIe root ports'
interrupts were routed to PIRQ E/F/G/H before, while actually all
PCIe downstream ports received INTx are routed to PIRQ A/B/C/D
directly and not configurable. Now we change this mapping so that
any external PCIe device can work correctly.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
show more ...
|
| a2d73fdb | 23-Jun-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Remove inline for lapic access routines
Remove inline for lapic access routines and expose lapic_read()
& lapic_write() as APIs to read/write lapic registers. Also move
stop_this_cpu() to mp_in
x86: Remove inline for lapic access routines
Remove inline for lapic access routines and expose lapic_read()
& lapic_write() as APIs to read/write lapic registers. Also move
stop_this_cpu() to mp_init.c as it has nothing to do with lapic.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
show more ...
|
| 3d232878 | 23-Jun-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Add I/O APIC register access routines
I/O APIC registers are addressed indirectly. Add io_apic_read() and
io_apic_write() routines to help register access. Two macros for I/O
APIC ID and versio
x86: Add I/O APIC register access routines
I/O APIC registers are addressed indirectly. Add io_apic_read() and
io_apic_write() routines to help register access. Two macros for I/O
APIC ID and version register offset are also added.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
show more ...
|
| df81749d | 23-Jun-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Reduce PIRQ routing table size
There is no need to populate multiple irq info entries with the same
bus number and device number, but with different interrupt pin. We
can use the same entry to
x86: Reduce PIRQ routing table size
There is no need to populate multiple irq info entries with the same
bus number and device number, but with different interrupt pin. We
can use the same entry to store all the 4 interrupt pin (INT A/B/C/D)
routing information to reduce the whole PIRQ routing table size.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
show more ...
|
| 8c38e4d0 | 23-Jun-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Ignore function number when writing PIRQ routing table
In fill_irq_info() pci device's function number is written into
the table, however this is not really necessary. The function
number can b
x86: Ignore function number when writing PIRQ routing table
In fill_irq_info() pci device's function number is written into
the table, however this is not really necessary. The function
number can be anything as OS doesn't care about this field,
neither does the PIRQ routing specification. Change to always
writing 0 as the function number.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
show more ...
|
| 9c235436 | 23-Jun-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Write correct bus number for the irq router
We should write correct bus number to the PIRQ routing table for the
irq router from device tree, instead of hard-coded zero.
Signed-off-by: Bin Men
x86: Write correct bus number for the irq router
We should write correct bus number to the PIRQ routing table for the
irq router from device tree, instead of hard-coded zero.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
show more ...
|
| 63d54a67 | 17-Jun-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Clean up lapic codes
This commit cleans up the lapic codes:
- Delete arch/x86/include/asm/lapic_def.h, and move register and bit
defines into arch/x86/include/asm/lapic.h
- Use MSR defines fr
x86: Clean up lapic codes
This commit cleans up the lapic codes:
- Delete arch/x86/include/asm/lapic_def.h, and move register and bit
defines into arch/x86/include/asm/lapic.h
- Use MSR defines from msr-index.h in enable_lapic() and disable_lapic()
- Remove unnecessary stuff like NEED_LAPIC, X86_GOOD_APIC and
CONFIG_AP_IN_SIPI_WAIT
- Move struct x86_cpu_priv defines to asm/arch-ivybridge/bd82x6x.h, as
it is not apic related and only used by ivybridge
- Fix coding convention issues
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
show more ...
|
| 61788e46 | 17-Jun-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Move lapic_setup() call into init_bsp()
Currently lapic_setup() is called before calling mp_init(), which
then calls init_bsp() where it calls enable_lapic(), which was
already enabled in lapic
x86: Move lapic_setup() call into init_bsp()
Currently lapic_setup() is called before calling mp_init(), which
then calls init_bsp() where it calls enable_lapic(), which was
already enabled in lapic_setup(). Hence move lapic_setup() call
into init_bsp() to avoid the duplication.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
show more ...
|
| 6e6f4ce4 | 17-Jun-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: Move MP initialization codes into a common place
Most of the MP initialization codes in arch/x86/cpu/baytrail/cpu.c is
common to all x86 processors, except detect_num_cpus() which varies
from c
x86: Move MP initialization codes into a common place
Most of the MP initialization codes in arch/x86/cpu/baytrail/cpu.c is
common to all x86 processors, except detect_num_cpus() which varies
from cpu to cpu. Move these to arch/x86/cpu/cpu.c and implement the
new 'get_count' method for baytrail and cpu_x86 drivers. Now we call
cpu_get_count() in mp_init() to get the number of CPUs.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
show more ...
|