x86: Fix up PIRQ routing table checksum earlier

PIRQ routing table checksum is fixed up in copy_pirq_routing_table(),
which is fine if we only write the configuration table once. But with
the SeaBIO

x86: Fix up PIRQ routing table checksum earlier

PIRQ routing table checksum is fixed up in copy_pirq_routing_table(),
which is fine if we only write the configuration table once. But with
the SeaBIOS case, when we write the table for the second time, the
checksum will be fixed up to zero per the checksum algorithm, which
is caused by the checksum field not being zero before fix up, since
the checksum has already been calculated in the first run.

To fix this, move the checksum fixup to create_pirq_routing_table(),
so that copy_pirq_routing_table() only does what its function name
suggests: copy the table to somewhere else.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

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x86: Call board_final_cleanup() in last_stage_init()

At present board_final_cleanup() is called before booting a Linux
kernel. This actually needs to be done before booting anything,
like SeaBIOS, V

x86: Call board_final_cleanup() in last_stage_init()

At present board_final_cleanup() is called before booting a Linux
kernel. This actually needs to be done before booting anything,
like SeaBIOS, VxWorks or Windows.

Move the call to last_stage_init() instead.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

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x86: qemu: rename qemu/acpi_table.c

Rename qemu/acpi_table.c to qemu/e820.c, because ACPI stuff is moved
to qfw core, this file only contains code for installing e820 table.

Signed-off-by: Miao Yan

x86: qemu: rename qemu/acpi_table.c

Rename qemu/acpi_table.c to qemu/e820.c, because ACPI stuff is moved
to qfw core, this file only contains code for installing e820 table.

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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cmd: qfw: bring ACPI generation code into qfw core

Loading ACPI table from QEMU's fw_cfg interface is not x86 specific
(ARM64 may also make use of it). So move the code to common place.

Signed-off-

cmd: qfw: bring ACPI generation code into qfw core

Loading ACPI table from QEMU's fw_cfg interface is not x86 specific
(ARM64 may also make use of it). So move the code to common place.

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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cmd: qfw: rename qemu_fw_cfg.[c|h] to qfw.[c|h]

Make file names consistent with CONFIG_QFW and CONFIG_CMD_QFW

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.c

cmd: qfw: rename qemu_fw_cfg.[c|h] to qfw.[c|h]

Make file names consistent with CONFIG_QFW and CONFIG_CMD_QFW

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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x86: qemu: add comment about qfw register endianness

This patch adds some comments about qfw register endianness for clarity.

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <

x86: qemu: add comment about qfw register endianness

This patch adds some comments about qfw register endianness for clarity.

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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x86: qemu: move x86 specific operations out of qfw core

The original implementation of qfw includes several x86 specific
operations, like directly calling outb/inb and using some inline
assembly cod

x86: qemu: move x86 specific operations out of qfw core

The original implementation of qfw includes several x86 specific
operations, like directly calling outb/inb and using some inline
assembly code which prevents it being ported to other architectures.

This patch adds callback functions and moves those to arch/x86/

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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x86: qemu: split qfw command interface and qfw core

This patch splits qfw command interface and qfw core function into two
files, and introduces a new Kconfig option (CONFIG_QFW) for qfw core.

Now

x86: qemu: split qfw command interface and qfw core

This patch splits qfw command interface and qfw core function into two
files, and introduces a new Kconfig option (CONFIG_QFW) for qfw core.

Now when qfw command interface is enabled, it will automatically select
qfw core. This patch also makes the ACPI table generation select
CONFIG_QFW.

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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cmd: qfw: remove qemu_fwcfg_free_files()

This patch is part of the qfw refactor work.

The qemu_fwcfg_free_files() function is only used in error handling in
ACPI table generation, let's not make th

cmd: qfw: remove qemu_fwcfg_free_files()

This patch is part of the qfw refactor work.

The qemu_fwcfg_free_files() function is only used in error handling in
ACPI table generation, let's not make this a core function and move it
to the right place.

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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x86: qemu: fix ACPI Kconfig options

CONFIG_GENENRATE_ACPI_TABLE controls the generation of ACPI table which
uses U-Boot's built-in methods and CONFIG_QEMU_ACPI_TABLE controls whether
to load ACPI ta

x86: qemu: fix ACPI Kconfig options

CONFIG_GENENRATE_ACPI_TABLE controls the generation of ACPI table which
uses U-Boot's built-in methods and CONFIG_QEMU_ACPI_TABLE controls whether
to load ACPI table from QEMU's fw_cfg interface.

But with commit "697ec431469ce0a4c2fc2c02d8685d907491af84 x86: qemu: Drop
our own ACPI implementation", there is only one way to support ACPI table
for QEMU targets which is the fw_cfg interface. Having two Kconfig options
for this purpose is not necessary any more, so this patch consolidates
the two.

Signed-off-by: Miao Yan <yanmiaobest@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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x86: qemu: Move qfw command over to cmd and add Kconfig entry

- Move the command portion of arch/x86/cpu/qemu/fw_cfg.c into
cmd/qemu_fw_cfg.c
- Move arch/x86/include/asm/fw_cfg.h to include/qemu_f

x86: qemu: Move qfw command over to cmd and add Kconfig entry

- Move the command portion of arch/x86/cpu/qemu/fw_cfg.c into
cmd/qemu_fw_cfg.c
- Move arch/x86/include/asm/fw_cfg.h to include/qemu_fw_cfg.h
- Rename ACPI table portion to arch/x86/cpu/qemu/acpi_table.c

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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x86: baytrail: Generate ACPI FADT/MADT tables

FADT/MADT tables are platform specific. Generate them for BayTrail.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium

x86: baytrail: Generate ACPI FADT/MADT tables

FADT/MADT tables are platform specific. Generate them for BayTrail.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

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x86: irq: Enable SCI on IRQ9

By default SCI is disabled after power on. ACTL is the register to
enable SCI and route it to PIC/APIC. To support both ACPI in PIC
mode and APIC mode, configure SCI to

x86: irq: Enable SCI on IRQ9

By default SCI is disabled after power on. ACTL is the register to
enable SCI and route it to PIC/APIC. To support both ACPI in PIC
mode and APIC mode, configure SCI to use IRQ9.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>

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x86: irq: Reserve IRQ9 for ACPI in PIC mode

Reserve IRQ9 which is to be used as SCI interrupt number
for ACPI in PIC mode.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr

x86: irq: Reserve IRQ9 for ACPI in PIC mode

Reserve IRQ9 which is to be used as SCI interrupt number
for ACPI in PIC mode.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>

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x86: Drop asm/acpi.h

Remove asm/acpi.h which is never used.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Sim

x86: Drop asm/acpi.h

Remove asm/acpi.h which is never used.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tested-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>

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dm: Rename disk uclass to ahci

This started as 'ahci' and was renamed to 'disk' during code review. But it
seems that this is too generic. Now that we have a 'blk' uclass, we can use
that as the gen

dm: Rename disk uclass to ahci

This started as 'ahci' and was renamed to 'disk' during code review. But it
seems that this is too generic. Now that we have a 'blk' uclass, we can use
that as the generic piece, and revert to ahci for this.

Signed-off-by: Simon Glass <sjg@chromium.org>

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x86: Correct typo of Miao Yan's email address

Miao Yan's email address is wrong in fw_cfg.c. Fix it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

x86: qemu: Drop our own ACPI implementation

Our own ACPI implementation (when CONFIG_QEMU_ACPI_TABLE is not set)
does not build anymore after x86 has been fully converted to DM PCI.
Instead of tryin

x86: qemu: Drop our own ACPI implementation

Our own ACPI implementation (when CONFIG_QEMU_ACPI_TABLE is not set)
does not build anymore after x86 has been fully converted to DM PCI.
Instead of trying to fix the build errors, given we now have the ACPI
support via QEMU's fw_cfg interface, which is a more reliable way to
generate correct ACPI tables than by ourselves, hence drop our own
ACPI implementation.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>

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arm: x86: Drop command-line code when CONFIG_CMDLINE is disabled

Update the link script to drop this code when not needed. This is only done
for two architectures at present.

Signed-off-by: Simon G

arm: x86: Drop command-line code when CONFIG_CMDLINE is disabled

Update the link script to drop this code when not needed. This is only done
for two architectures at present.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Rini <trini@konsulko.com>

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x86: Support a chained-boot development flow

Sometimes it is useful to jump into U-Boot directly from coreboot or UEFI
without any 16-bit init. This can help during development by allowing U-Boot
to

x86: Support a chained-boot development flow

Sometimes it is useful to jump into U-Boot directly from coreboot or UEFI
without any 16-bit init. This can help during development by allowing U-Boot
to avoid doing all the init required by the platform.

U-Boot expects its GDT to be set up correctly by its 16-bit code. If
coreboot doesn't do this (because it hasn't run the payload setup code yet)
then this won't happen.

In this case we cannot rely on the GDT settings. U-Boot will hang or crash
if these are wrong. Provide a development-only option to set up the GDT
correctly. This is just a hack so you can jump to U-Boot from any stage of
coreboot, not just at the end.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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x86: ivybridge: Convert to use the common SDRAM code

Adjust the existing implementation to use the new common SDRAM init code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <b

x86: ivybridge: Convert to use the common SDRAM code

Adjust the existing implementation to use the new common SDRAM init code.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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x86: Add common SDRAM-init code

The code to call the memory reference code is common to several Intel CPUs.
Add common code for performing this init. Intel calls this 'Pre-EFI-Init'
(PEI), where EFI

x86: Add common SDRAM-init code

The code to call the memory reference code is common to several Intel CPUs.
Add common code for performing this init. Intel calls this 'Pre-EFI-Init'
(PEI), where EFI stands for Extensible Firmware Interface.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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x86: Move common PCH code into a common place

The SATA indexed register write functions are common to several Intel PCHs.
Move this into a common location.

Signed-off-by: Simon Glass <sjg@chromium.

x86: Move common PCH code into a common place

The SATA indexed register write functions are common to several Intel PCHs.
Move this into a common location.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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x86: Add a function to set the IOAPIC ID

Add a function to set the ID in the IOAPIC.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

x86: broadwell: Add support for high-speed I/O lane with ME

Provide a way to determine the HSIO (high-speed I/O) version supported by
the Intel Management Engine (ME) implementation on the platform.

x86: broadwell: Add support for high-speed I/O lane with ME

Provide a way to determine the HSIO (high-speed I/O) version supported by
the Intel Management Engine (ME) implementation on the platform.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Bin Meng <bmeng.cn@gmail.com>

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