History log of /rk3399_rockchip-uboot/arch/x86/cpu/Makefile (Results 26 – 50 of 70)
Revision Date Author Comments
# 9c7dea60 25-May-2015 Bin Meng <bmeng.cn@gmail.com>

x86: Refactor PIRQ routing support

PIRQ routing is pretty much common in Intel chipset. It has several
PIRQ links (normally 8) and corresponding registers (either in PCI
configuration space or memor

x86: Refactor PIRQ routing support

PIRQ routing is pretty much common in Intel chipset. It has several
PIRQ links (normally 8) and corresponding registers (either in PCI
configuration space or memory-mapped IBASE) to configure the legacy
8259 IRQ vector mapping. Refactor current Queensbay PIRQ routing
support using device tree and move it to a common place, so that we
can easily add PIRQ routing support on a new platform.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

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# a65b25d1 07-May-2015 Bin Meng <bmeng.cn@gmail.com>

x86: Support QEMU x86 targets

This commit introduces the initial U-Boot support for QEMU x86 targets.
U-Boot can boot from coreboot as a payload, or directly without coreboot.

Signed-off-by: Bin Me

x86: Support QEMU x86 targets

This commit introduces the initial U-Boot support for QEMU x86 targets.
U-Boot can boot from coreboot as a payload, or directly without coreboot.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Tested-by: Simon Glass <sjg@chromium.org>
Merged in patch 'x86: qemu: Add CMD_NET to qemu-x86_defconfig
https://patchwork.ozlabs.org/patch/479745/

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# 45b5a378 30-Apr-2015 Simon Glass <sjg@chromium.org>

x86: Add multi-processor init

Most modern x86 CPUs include more than one CPU core. The OS normally requires
that these 'Application Processors' (APs) be brought up by the boot loader.
Add the requir

x86: Add multi-processor init

Most modern x86 CPUs include more than one CPU core. The OS normally requires
that these 'Application Processors' (APs) be brought up by the boot loader.
Add the required support to U-Boot to init additional APs.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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# e1cc4d31 24-Feb-2015 Albert ARIBAUD <albert.u.boot@aribaud.net>

Merge remote-tracking branch 'u-boot/master' into 'u-boot-arm/master'


# e72d3443 13-Feb-2015 Stefano Babic <sbabic@denx.de>

Merge branch 'master' of git://git.denx.de/u-boot


# db7a7dee 10-Feb-2015 Tom Rini <trini@ti.com>

Merge branch 'master' of git://git.denx.de/u-boot-x86


# ef46bea0 02-Feb-2015 Bin Meng <bmeng.cn@gmail.com>

x86: Enable the Intel quark/galileo build

Make the Intel quark/galileo support avaiable in Kconfig and Makefile.
With this patch, we can generate u-boot.rom for Intel galileo board.

Signed-off-by:

x86: Enable the Intel quark/galileo build

Make the Intel quark/galileo support avaiable in Kconfig and Makefile.
With this patch, we can generate u-boot.rom for Intel galileo board.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>

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# 3a1a18ff 28-Jan-2015 Simon Glass <sjg@chromium.org>

x86: Add support for Intel Minnowboard Max

This is a relatively low-cost x86 board in a small form factor. The main
peripherals are uSD, USB, HDMI, Ethernet and SATA. It uses an Atom 3800
series CPU

x86: Add support for Intel Minnowboard Max

This is a relatively low-cost x86 board in a small form factor. The main
peripherals are uSD, USB, HDMI, Ethernet and SATA. It uses an Atom 3800
series CPU. So far only the dual core 2GB variant is supported.

This uses the existing FSP support. Binary blobs are required to make this
board work. The microcode update is included as a patch (all 3000 lines of
it).

Change-Id: I0088c47fe87cf08ae635b343d32c332269062156
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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# 5f88ed5c 13-Jan-2015 Tom Rini <trini@ti.com>

Merge git://git.denx.de/u-boot-x86


# aff2523f 01-Jan-2015 Simon Glass <sjg@chromium.org>

x86: Add support for MTRRs

Memory Type Range Registers are used to tell the CPU whether memory is
cacheable and if so the cache write mode to use.

Clean up the existing header file to follow style,

x86: Add support for MTRRs

Memory Type Range Registers are used to tell the CPU whether memory is
cacheable and if so the cache write mode to use.

Clean up the existing header file to follow style, and remove the unneeded
code.

These can speed up booting so should be supported. Add these to global_data
so they can be requested while booting. We will apply the changes during
relocation (in a later commit).

Signed-off-by: Simon Glass <sjg@chromium.org>

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# 4e0114d9 30-Dec-2014 Stefano Babic <sbabic@denx.de>

Merge branch 'master' of git://git.denx.de/u-boot

Signed-off-by: Stefano Babic <sbabic@denx.de>


# d8046ff0 19-Dec-2014 Tom Rini <trini@ti.com>

Merge git://git.denx.de/u-boot-x86


# 240a79d9 17-Dec-2014 Bin Meng <bmeng.cn@gmail.com>

x86: Enable the queensbay cpu directory build

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>


# f4e7e2d1 01-Dec-2014 Tom Rini <trini@ti.com>

Merge git://git.denx.de/u-boot-x86


# 0c9075e9 25-Nov-2014 Simon Glass <sjg@chromium.org>

x86: Add LAPIC setup code

Add code to set up the Local Advanced Peripheral Interrupt Controller.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>


# 18739e2c 15-Nov-2014 Simon Glass <sjg@chromium.org>

x86: Add Intel speedstep and turbo mode code

Intel chips have a turbo mode where they can run faster for a short period
until they reach thermal limits. Add code to adjust and query this feature.

S

x86: Add Intel speedstep and turbo mode code

Intel chips have a turbo mode where they can run faster for a short period
until they reach thermal limits. Add code to adjust and query this feature.

Signed-off-by: Simon Glass <sjg@chromium.org>

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# 2f6d42b9 25-Nov-2014 Simon Glass <sjg@chromium.org>

x86: Add ivybridge directory to Makefile

It is now required to add subdirectories in the x86 cpu Makefile. Add this
to fix a build breakage for chromebook_link.

Signed-off-by: Simon Glass <sjg@chro

x86: Add ivybridge directory to Makefile

It is now required to add subdirectories in the x86 cpu Makefile. Add this
to fix a build breakage for chromebook_link.

Signed-off-by: Simon Glass <sjg@chromium.org>

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# 746667f1 24-Nov-2014 Tom Rini <trini@ti.com>

Merge git://git.denx.de/u-boot-x86

Conflicts:
arch/x86/cpu/Makefile

Signed-off-by: Tom Rini <trini@ti.com>


# 37c9940a 13-Nov-2014 Masahiro Yamada <yamada.m@jp.panasonic.com>

x86: use CONFIG_SYS_COREBOOT to descend into coreboot/ directory

The references of CONFIG_SYS_COREBOOT in arch/x86/cpu/coreboot/Makefile
are redundant because the build system descends into the dire

x86: use CONFIG_SYS_COREBOOT to descend into coreboot/ directory

The references of CONFIG_SYS_COREBOOT in arch/x86/cpu/coreboot/Makefile
are redundant because the build system descends into the directory
only when CONFIG_SYS_COREBOOT is defined.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Simon Glass <sjg@chromium.org>
Acked-by: Simon Glass <sjg@chromium.org>

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# 165ecd26 13-Nov-2014 Masahiro Yamada <yamada.m@jp.panasonic.com>

kbuild: Descend into SOC directory from CPU directory

Some CPUs of some architectures have SOC directories.
At present, the build system directly descends into SOC directories
from the top Makefile,

kbuild: Descend into SOC directory from CPU directory

Some CPUs of some architectures have SOC directories.
At present, the build system directly descends into SOC directories
from the top Makefile, but it should generally descend into each
directory from its parent directory.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

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# d188b18f 13-Nov-2014 Simon Glass <sjg@chromium.org>

x86: Refactor PCI to permit alternate init

We want access PCI earlier in the init sequence, so refactor the code so
that it does not require use of a BSS variable to work. This will allow us
to use

x86: Refactor PCI to permit alternate init

We want access PCI earlier in the init sequence, so refactor the code so
that it does not require use of a BSS variable to work. This will allow us
to use early malloc() to store information about a PCI hose.

Common PCI code moves to arch/x86/cpu/pci.c and a new
board_pci_setup_hose() function is provided by boards to set up the (single)
hose used by that board.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

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# 2c54cb55 29-Oct-2014 Tom Rini <trini@ti.com>

Merge git://git.denx.de/u-boot-x86


# 200182a7 10-Oct-2014 Simon Glass <sjg@chromium.org>

x86: Add support for starting 64-bit kernel

Add code to jump to a 64-bit Linux kernel. We need to set up a flat page
table structure, a new GDT and then go through a few hoops in the right
order.

S

x86: Add support for starting 64-bit kernel

Add code to jump to a 64-bit Linux kernel. We need to set up a flat page
table structure, a new GDT and then go through a few hoops in the right
order.

Signed-off-by: Simon Glass <sjg@chromium.org>

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# fb00601e 16-Oct-2014 Bin Meng <bmeng.cn@gmail.com>

x86: Fix rom version build with CONFIG_X86_RESET_VECTOR

When building U-Boot with CONFIG_X86_RESET_VECTOR, the linking
process misses the resetvec.o and start16.o so it cannot generate
the rom versi

x86: Fix rom version build with CONFIG_X86_RESET_VECTOR

When building U-Boot with CONFIG_X86_RESET_VECTOR, the linking
process misses the resetvec.o and start16.o so it cannot generate
the rom version of U-Boot. The arch/x86/cpu/Makefile is updated to
pull them into the final linking process.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

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# 3954b739 21-Oct-2013 Masahiro Yamada <yamada.m@jp.panasonic.com>

x86: convert makefiles to Kbuild style

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Simon Glass <sjg@chromium.org>


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