Add bootscript support to esbc_validate.

1. Default environment will be used for secure boot flow
which can't be edited or saved.
2. Command for secure boot is predefined in the default
environmen

Add bootscript support to esbc_validate.

1. Default environment will be used for secure boot flow
which can't be edited or saved.
2. Command for secure boot is predefined in the default
environment which will run on autoboot (and autoboot is
the only option allowed in case of secure boot) and it
looks like this:
#define CONFIG_SECBOOT \
"setenv bs_hdraddr 0xe8e00000;" \
"esbc_validate $bs_hdraddr;" \
"source $img_addr;" \
"esbc_halt;"
#endif
3. Boot Script can contain esbc_validate commands and bootm command.
Uboot source command used in default secure boot command will
run the bootscript.
4. Command esbc_halt added to ensure either bootm executes
after validation of images or core should just spin.

Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

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powerpc/t2080: enable erratum_a007186 for t2080 rev1.1

T2080 rev1.1 also needs erratum a007186.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.c

powerpc/t2080: enable erratum_a007186 for t2080 rev1.1

T2080 rev1.1 also needs erratum a007186.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

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SECURE_BOOT : enable esbc_validate command for powerpc and arm platforms.

esbc_validate command uses various IP Blocks: Security Monitor, CAAM block
and SFP registers. Hence the respective CONFIG's

SECURE_BOOT : enable esbc_validate command for powerpc and arm platforms.

esbc_validate command uses various IP Blocks: Security Monitor, CAAM block
and SFP registers. Hence the respective CONFIG's are enabled.

Apart from these CONFIG_SHA_PROG_HW_ACCEL and CONFIG_RSA are also enabled.

Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

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fsl_sfp : Move ccsr_sfp_regs definition to common include

Freescale sfp has been used for mpc8xxx. It will be used
for ARM-based SoC as well. This patch moves the CCSR defintion of
sfp_regs to commo

fsl_sfp : Move ccsr_sfp_regs definition to common include

Freescale sfp has been used for mpc8xxx. It will be used
for ARM-based SoC as well. This patch moves the CCSR defintion of
sfp_regs to common include. This patch also defines ccsr_sfp_regs
definition for newer versions of SFP.

Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

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powerpc: 85xx: Modify CONFIG_USB_MAX_CONTROLLER_COUNT for P1022DS

Modify CONFIG_USB_MAX_CONTROLLER_COUNT value to 1 on P1022DS.
As ETSEC2 and USB2 are muxed; thus if ETSEC2 is enabled, the
system bu

powerpc: 85xx: Modify CONFIG_USB_MAX_CONTROLLER_COUNT for P1022DS

Modify CONFIG_USB_MAX_CONTROLLER_COUNT value to 1 on P1022DS.
As ETSEC2 and USB2 are muxed; thus if ETSEC2 is enabled, the
system bus hangs on USB2 if ETSEC2 is enabled but "usb start"
command is issued. Hence making default controller count to 1
to avoid system hang.

Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com>
Reviewed-by: Yusong Sun <yorksun@freescale.com>

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powerpc/mpc85xx: Add DSP side awareness for Freescale Heterogeneous SoCs

The code provides framework for heterogeneous multicore chips based on StarCore
and Power Architecture which are chasis-2 com

powerpc/mpc85xx: Add DSP side awareness for Freescale Heterogeneous SoCs

The code provides framework for heterogeneous multicore chips based on StarCore
and Power Architecture which are chasis-2 compliant, like B4860 and B4420

It will make u-boot recognize all non-ppc cores and peripherals like
SC3900/DSP CPUs, MAPLE, CPRI and print their configuration in u-boot logs.
Example boot logs of B4860QDS:

U-Boot 2015.01-00232-geef6e36-dirty (Jan 19 2015 - 11:58:45)

CPU0: B4860E, Version: 2.2, (0x86880022)
Core: e6500, Version: 2.0, (0x80400120)
Clock Configuration:
CPU0:1600 MHz, CPU1:1600 MHz, CPU2:1600 MHz, CPU3:1600 MHz,
DSP CPU0:1200 MHz, DSP CPU1:1200 MHz, DSP CPU2:1200 MHz, DSP CPU3:1200 MHz,
DSP CPU4:1200 MHz, DSP CPU5:1200 MHz,
CCB:666.667 MHz,
DDR:933.333 MHz (1866.667 MT/s data rate) (Asynchronous), IFC:166.667 MHz
CPRI:600 MHz
MAPLE:600 MHz, MAPLE-ULB:800 MHz, MAPLE-eTVPE:1000 MHz
FMAN1: 666.667 MHz
QMAN: 333.333 MHz

Top level changes include:
(1) Top level CONFIG to identify HETEROGENUOUS clusters
(2) CONFIGS for SC3900/DSP components
(3) Global structures like "cpu_type" and "MPC85xx_SYS_INFO"
updated for dsp cores and other components
(3) APIs to get DSP num cores and their Mask like:
cpu_dsp_mask, cpu_num_dspcores etc same as that of PowerPC
(5) Code to fetch and print SC cores and other heterogenous
device's frequencies
(6) README added for the same

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

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powerpc: Add linkage.h file

This permits us to use linux/linkage.h on PowerPC machines.

Signed-off-by: Simon Glass <sjg@chromium.org>

ppc: amcc: Omit unneeded ns16550 CONFIG if using driver model

This comes from the device tree or a call to get_uart_clock().

Signed-off-by: Simon Glass <sjg@chromium.org>

powerpc: ppc4xx: Add a gpio.h header file

This is required at present for device tree control. The ppc4xx does support
GPIOs but does not seem to have a proper driver. So this file is empty.

Signed

powerpc: ppc4xx: Add a gpio.h header file

This is required at present for device tree control. The ppc4xx does support
GPIOs but does not seem to have a proper driver. So this file is empty.

Signed-off-by: Simon Glass <sjg@chromium.org>

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crypto/fsl: Add fixup for crypto node

Era property is added in the crypto node in device tree.
Move the code to do so from arch/powerpc/mpc8xxx/fdt.c to
drivers/sec/sec.c so that it can be used acro

crypto/fsl: Add fixup for crypto node

Era property is added in the crypto node in device tree.
Move the code to do so from arch/powerpc/mpc8xxx/fdt.c to
drivers/sec/sec.c so that it can be used across arm and
powerpc platforms having crypto node.

Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
[York Sun: Fix commit message indentation]
Reviewed-by: York Sun <yorksun@freescale.com>

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arch/powerpc: Add SGMII support for the L2 Switch ports

Some Freescale SoCs like T1020 and T1040 have an integrated
L2 Switch. The L2 Switch ports may be connected to Ethernet PHYs
over SGMII and QS

arch/powerpc: Add SGMII support for the L2 Switch ports

Some Freescale SoCs like T1020 and T1040 have an integrated
L2 Switch. The L2 Switch ports may be connected to Ethernet PHYs
over SGMII and QSGMII.

Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

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arch/powerpc: Fix mapping of Freescale SerDes protocols

The number of supported serdes protocols on Freescale SoCs
has increased over time. Until now, an u64 variable have been
initialized on boot w

arch/powerpc: Fix mapping of Freescale SerDes protocols

The number of supported serdes protocols on Freescale SoCs
has increased over time. Until now, an u64 variable have been
initialized on boot with the configured protocols. However,
since this number has increased (enum srds_prtcl has more
than 64 values), 64 bits are no longer sufficient to hold track
of all the configured protocols.
This patch replaces the u64 map values with static arrays.
To keep track of the number of serdes protocols, the
SERDES_PRCTL_COUNT vale has been added at the end of
enum srds_prtcl. This value must always be the last one.

Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

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powerpc/mpc85xx: Define PBI Flash Base for C29XPCIE Secure Boot

CONFIG_SYS_PBI_FLASH_BASE is defined for Secure Boot on C29X

Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by:

powerpc/mpc85xx: Define PBI Flash Base for C29XPCIE Secure Boot

CONFIG_SYS_PBI_FLASH_BASE is defined for Secure Boot on C29X

Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

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powerpc: mpc85xx: Add dummy gpio.h to enable CONFIG_OF_CONTROL

If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled.
It includes <asm/gpio.h> and then <asm/gpio.h> includes
<asm/arch/gpio.h>.

powerpc: mpc85xx: Add dummy gpio.h to enable CONFIG_OF_CONTROL

If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled.
It includes <asm/gpio.h> and then <asm/gpio.h> includes
<asm/arch/gpio.h>. As a result, all the SoCs that enable
CONFIG_OF_CONTROL must have <asm/arch/gpio.h>.

The right fix would be to split the lib/fdtdec.c to remove
dependency on GPIO.

This commit adds a dummy <asm/arch/gpio.h> to support OF_CONTROL
for mpc85xx platform. A file mpc85xx_gpio.h exists in
arch/powerpc/include/asm. The defintions in that file conflict
with the ones in asm-generic/gpio.h. Hence a dummy header file
has been added. This will be removed after FDT-GPIO stuff is
fixed correctly.

Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

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powerpc: 74xx_7xx: remove 74xx_7xx cpu support

All the 74xx_7xx boards are still non-generic boards:
P3G4, ZUMA, ppmc7xx, ELPPC, mpc7448hpc2

Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Stefan R

powerpc: 74xx_7xx: remove 74xx_7xx cpu support

All the 74xx_7xx boards are still non-generic boards:
P3G4, ZUMA, ppmc7xx, ELPPC, mpc7448hpc2

Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: York Sun <yorksun@freescale.com>
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Nye Liu <nyet@zumanetworks.com>
Cc: Roy Zang <tie-fei.zang@freescale.com>

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