powerpc/mpc85xx: Added B4460 support

B4460 differs from B4860 only in number of CPU cores,
hence used existing support for B4860.
B4460 has 2 PPC cores whereas B4860 has 4 PPC cores.

Signed-off-by:

powerpc/mpc85xx: Added B4460 support

B4460 differs from B4860 only in number of CPU cores,
hence used existing support for B4860.
B4460 has 2 PPC cores whereas B4860 has 4 PPC cores.

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Sandeep Singh <Sandeep@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>

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Merge remote-tracking branch 'u-boot/master' into test

Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

powerpc/85xx: add T4080 SoC support

The T4080 SoC is a low-power version of the T4160.
T4080 combines 4 dual-threaded Power Architecture e6500
cores with single cluster and two memory complexes.

Si

powerpc/85xx: add T4080 SoC support

The T4080 SoC is a low-power version of the T4160.
T4080 combines 4 dual-threaded Power Architecture e6500
cores with single cluster and two memory complexes.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>

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Merge branch 'master' of git://git.denx.de/u-boot-arm into master

Conflicts:
arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg
arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg

Signed-off-by: Stefano Babic

Merge branch 'master' of git://git.denx.de/u-boot-arm into master

Conflicts:
arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg
arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg

Signed-off-by: Stefano Babic <sbabic@denx.de>

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powerpc: mpc8260: consolidate CONFIG_MPC8260 and CONFIG_8260

Before this commit, CONFIG_MPC8260 and CONFIG_8260
were used mixed-up.

All boards with mpc8260 cpu defined both of them:
- CONFIG_MPC8

powerpc: mpc8260: consolidate CONFIG_MPC8260 and CONFIG_8260

Before this commit, CONFIG_MPC8260 and CONFIG_8260
were used mixed-up.

All boards with mpc8260 cpu defined both of them:
- CONFIG_MPC8260 was defined in board config headers
and include/common.h
- CONFIG_8260 was defined arch/powerpc/cpu/mpc8260/config.mk

We do not need to have both of them.
This commit keeps only CONFIG_MPC8260.

This commit does:
- Delete CONFIG_8260 and CONFIG_MPC8260 definition
in config headers and include/common.h
- Rename CONFIG_8260 to CONFIG_MPC8260
in arch/powerpc/cpu/mpc8260/config.mk.
- Rename #ifdef CONFIG_8260 to #ifdef CONFIG_MPC8260

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Cc: Wolfgang Denk <wd@denx.de>

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Merge branch 'u-boot/master' into 'u-boot-arm/master'

Conflicts:
arch/arm/cpu/armv7/rmobile/Makefile
doc/README.scrapyard

Needed manual fix:
arch/arm/cpu/armv7/omap-common/Makefile
board/compul

Merge branch 'u-boot/master' into 'u-boot-arm/master'

Conflicts:
arch/arm/cpu/armv7/rmobile/Makefile
doc/README.scrapyard

Needed manual fix:
arch/arm/cpu/armv7/omap-common/Makefile
board/compulab/cm_t335/u-boot.lds

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Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

powerpc/mpc85xx: Add T2080/T2081 SoC support

Add support for Freescale T2080/T2081 SoC.

T2080 includes the following functions and features:
- Four dual-threads 64-bit Power architecture e6500 core

powerpc/mpc85xx: Add T2080/T2081 SoC support

Add support for Freescale T2080/T2081 SoC.

T2080 includes the following functions and features:
- Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
- 2MB L2 cache and 512KB CoreNet platform cache (CPC)
- Hierarchical interconnect fabric
- One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
- Data Path Acceleration Architecture (DPAA) incorporating acceleration
- 16 SerDes lanes up to 10.3125 GHz
- 8 mEMACs for network interfaces (four 1Gbps MACs and four 10Gbps/1Gbps MACs)
- High-speed peripheral interfaces
- Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
- Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz
- Additional peripheral interfaces
- Two serial ATA (SATA 2.0) controllers
- Two high-speed USB 2.0 controllers with integrated PHY
- Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC)
- Enhanced serial peripheral interface (eSPI)
- Four I2C controllers
- Four 2-pin UARTs or two 4-pin UARTs
- Integrated Flash Controller supporting NAND and NOR flash
- Three eight-channel DMA engines
- Support for hardware virtualization and partitioning enforcement
- QorIQ Platform's Trust Architecture 2.0

Differences between T2080 and T2081:
Feature T2080 T2081
1G Ethernet numbers: 8 6
10G Ethernet numbers: 4 2
SerDes lanes: 16 8
Serial RapidIO,RMan: 2 no
SATA Controller: 2 no
Aurora: yes no
SoC Package: 896-pins 780-pins

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Acked-by: York Sun <yorksun@freescale.com>

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include: delete include/linux/config.h

Linux Kernel abolished include/linux/config.h long time ago.
(around version v2.6.18..v2.6.19)

We don't need to provide Linux copatibility any more.

This com

include: delete include/linux/config.h

Linux Kernel abolished include/linux/config.h long time ago.
(around version v2.6.18..v2.6.19)

We don't need to provide Linux copatibility any more.

This commit deletes include/linux/config.h
and fixes source files not to include this.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>

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ppc4xx: Remove support for PPC405CR CPUs

This patch removes support for the APM 405CR CPU.
This CPU is EOL and no board uses this chip.

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>

Merge branch 'master' of git://git.denx.de/u-boot-i2c

fsl_i2c: add workaround for the erratum I2C A004447

This workaround is for the erratum I2C A004447. Device reference
manual provides a scheme that allows the I2C master controller
to generate nine S

fsl_i2c: add workaround for the erratum I2C A004447

This workaround is for the erratum I2C A004447. Device reference
manual provides a scheme that allows the I2C master controller
to generate nine SCL pulses, which enable an I2C slave device
that held SDA low to release SDA. However, due to this erratum,
this scheme no longer works. In addition, when I2C is used as
a source of the PBL, the state machine is not able to recover.

At the same time, delete the reduplicative definition of SVR_VER
and SVR_REV. The SVR_REV is the low 8 bits rather than the low 16
bits of svr. And we use the CONFIG_SYS_FSL_A004447_SVR_REV macro
instead of hard-code value 0x10, 0x11 and 0x20.

The CONFIG_SYS_FSL_A004447_SVR_REV = 0x00 represents that one
version of platform has this I2C errata. So enable this errata
by IS_SVR_REV(svr, maj, min) function.

Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: Heiko Schocher <hs@denx.de>

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Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

powerpc/85xx: Add C29x SoC support

The Freescale C29x family is a high performance crypto co-processor.
It combines a single e500v2 core with necessary SEC engine. There're
three SoC types(C291, C29

powerpc/85xx: Add C29x SoC support

The Freescale C29x family is a high performance crypto co-processor.
It combines a single e500v2 core with necessary SEC engine. There're
three SoC types(C291, C292, C293) with the following features:

- 512K L2 Cache/SRAM and 512 KB platform SRAM
- DDR3/DDR3L 32bit DDR controller
- One PCI express (x1, x2, x4) Gen 2.0 Controller
- Trust Architecture 2.0
- SEC6.0 engine

Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Po Liu <Po.Liu@freescale.com>

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Merge branch 'u-boot/master' into 'u-boot-arm/master'

Conflicts:
common/cmd_fpga.c
drivers/usb/host/ohci-at91.c

powerpc/chassis2: Change core numbering scheme

To align with chassis generation 2 spec, all cores are numbered in sequence.
The cores may reside across multiple clusters. Each cluster has zero to fo

powerpc/chassis2: Change core numbering scheme

To align with chassis generation 2 spec, all cores are numbered in sequence.
The cores may reside across multiple clusters. Each cluster has zero to four
cores. The first available core is numbered as core 0. The second available
core is numbered as core 1 and so on.

Core clocks are generated by each clusters. To identify the cluster of each
core, topology registers are examined.

Cluster clock registers are reorganized to be easily indexed.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

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powerpc/mpc8xxx: Add T1040 and variant SoCs

T1040 and variants have e5500 cores and are compliant to QorIQ Chassis
Generation 2. The major difference between T1040 and its variants is the
number of

powerpc/mpc8xxx: Add T1040 and variant SoCs

T1040 and variants have e5500 cores and are compliant to QorIQ Chassis
Generation 2. The major difference between T1040 and its variants is the
number of cores and the number of L2 switch ports.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

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Add e6500 L2 replacement policy selection

This is compile-time config.

Signed-off-by: James Yang <James.Yang@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xx

powerpc/mpc85xx: Add T4160 SoC

T4160 SoC is low power version of T4240. The T4160 combines eight dual
threaded Power Architecture e6500 cores and two memory complexes (CoreNet
platform cache and DDR

powerpc/mpc85xx: Add T4160 SoC

T4160 SoC is low power version of T4240. The T4160 combines eight dual
threaded Power Architecture e6500 cores and two memory complexes (CoreNet
platform cache and DDR3 memory controller) with the same high-performance
datapath acceleration, networking, and peripheral bus interfaces.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

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powerpc/mpc85xx: Add definitions for HDBCR registers

Makes it a bit easier to see if we've properly set them. While
we're in there, modify the accesses to HDBCR0 and HDBCR1 to actually
use those de

powerpc/mpc85xx: Add definitions for HDBCR registers

Makes it a bit easier to see if we've properly set them. While
we're in there, modify the accesses to HDBCR0 and HDBCR1 to actually
use those definitions.

Signed-off-by: Andy Fleming <afleming@freescale.com>

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Merge branch 'master' of git://git.denx.de/u-boot-arm

Merge branch 'master' of git://git.denx.de/u-boot

powerpc/mpc85xx: Add BSC9132/BSC9232 processor support

The BSC9132 is a highly integrated device that targets the evolving
Microcell, Picocell, and Enterprise-Femto base station market subsegments.

powerpc/mpc85xx: Add BSC9132/BSC9232 processor support

The BSC9132 is a highly integrated device that targets the evolving
Microcell, Picocell, and Enterprise-Femto base station market subsegments.

The BSC9132 device combines Power Architecture e500 and DSP StarCore SC3850
core technologies with MAPLE-B2P baseband acceleration processing elements
to address the need for a high performance, low cost, integrated solution
that handles all required processing layers without the need for an
external device except for an RF transceiver or, in a Micro base station
configuration, a host device that handles the L3/L4 and handover between
sectors.

The BSC9132 SoC includes the following function and features:
- Power Architecture subsystem including two e500 processors with
512-Kbyte shared L2 cache
- Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2
cache
- 32 Kbyte of shared M3 memory
- The Multi Accelerator Platform Engine for Pico BaseStation Baseband
Processing (MAPLE-B2P)
- Two DDR3/3L memory interfaces with 32-bit data width (40 bits including
ECC), up to 1333 MHz data rate
- Dedicated security engine featuring trusted boot
- Two DMA controllers
- OCNDMA with four bidirectional channels
- SysDMA with sixteen bidirectional channels
- Interfaces
- Four-lane SerDes PHY
- PCI Express controller complies with the PEX Specification-Rev 2.0
- Two Common Public Radio Interface (CPRI) controller lanes
- High-speed USB 2.0 host and device controller with ULPI interface
- Enhanced secure digital (SD/MMC) host controller (eSDHC)
- Antenna interface controller (AIC), supporting four industry
standard JESD207/four custom ADI RF interfaces
- ADI lanes support both full duplex FDD support & half duplex TDD
- Universal Subscriber Identity Module (USIM) interface that
facilitates communication to SIM cards or Eurochip pre-paid phone
cards
- Two DUART, two eSPI, and two I2C controllers
- Integrated Flash memory controller (IFC)
- GPIO
- Sixteen 32-bit timers

Signed-off-by: Naveen Burmi <NaveenBurmi@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

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