| 9cdfe281 | 18-Jul-2011 |
Becky Bruce <beckyb@kernel.crashing.org> |
powerpc/mpc85xx: Add clear_ddr_tlbs function
This is useful when we just want to wipe out the TLBs. There's currently
a function that resets the ddr tlbs to a different value; it is changed to
util
powerpc/mpc85xx: Add clear_ddr_tlbs function
This is useful when we just want to wipe out the TLBs. There's currently
a function that resets the ddr tlbs to a different value; it is changed to
utilize this function. The new function can be used in conjunction with
setup_ddr_tlbs() for a board to temporarily map/unmap the DDR address
range as needed.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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| ffadc441 | 03-May-2011 |
Timur Tabi <timur@freescale.com> |
fman: insert the Fman firmware into the device tree
The Fman device tree node binding allows for the entire Fman firmware binary
data to be embedded in the device tree. This eliminates the need to
fman: insert the Fman firmware into the device tree
The Fman device tree node binding allows for the entire Fman firmware binary
data to be embedded in the device tree. This eliminates the need to have
NOR flash mapped to Linux just so that the Fman driver can see the firmware.
The location of the Fman firmware is taken from the 'fman_ucode' environment
variable.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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| 26002826 | 29-Apr-2011 |
Timur Tabi <timur@freescale.com> |
powerpc/85xx: remove SERDES4 soft-reset work-around
Some P4080 rev1 errata work-arounds, notably erratum SERDES4, required a
bank soft-reset after the bank was configured and enabled, even though
en
powerpc/85xx: remove SERDES4 soft-reset work-around
Some P4080 rev1 errata work-arounds, notably erratum SERDES4, required a
bank soft-reset after the bank was configured and enabled, even though
enabling a bank causes it to reset. Because the reset was required for
multiple errata, it was not properly enclosed in an #ifdef, and so was
not removed with all the other rev1 errata work-arounds.
Erratum SERDES-8 says that the clocks for bank 3 needs to be enabled if
bank 2 is enabled, but this was not being done for SERDES protocols 0xF
and 0x10. The bank reset also happened to enable bank 3 (apparently an
undocumented feature). Simply removing the reset breaks these two
protocols.
It turns out that every time we call enable_bank(), we do want at least
one lane of the bank enabled, either because the bank is supposed to be
enabled, or because we need the clock from that bank enabled.
For erratum SERDES-A001, we don't want to modify srds_lpd_b[] when we
call enable_bank(), because that array is used elsewhere to determine if
the bank is available.
Note that the side effect of these changes is that the work-arounds for
these two errata are now linked. Specifically, if SERDES-A001 is
enabled, then we need SERDES-8 enabled as well.
Because this was the only SERDES bank soft-reset, there is no need to
implement a work-around for erratum SERDES-A003.
Also fix an off-by-one error in a printf().
Signed-off-by: Timur Tabi <timur@freescale.com>
Acked-by: Ed Swarthout <swarthou@freescale.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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| 4c99cb91 | 27-Jun-2011 |
York Sun <yorksun@freescale.com> |
powerpc/mpc8xxx: fix DDR data width checking
Checking width before setting DDR controller. SPD for DDR1 and DDR2 has
data width and primary sdram width. The latter one has different meaning
for DDR3
powerpc/mpc8xxx: fix DDR data width checking
Checking width before setting DDR controller. SPD for DDR1 and DDR2 has
data width and primary sdram width. The latter one has different meaning
for DDR3.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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| f2d264b6 | 07-Jun-2011 |
York Sun <yorksun@freescale.com> |
powerpc/mpc8xxx: Adding fallback to raw timing on supported boards
In case of empty SPD or checksum error, fallback to raw timing on
supported boards.
Signed-off-by: York Sun <yorksun@freescale.com
powerpc/mpc8xxx: Adding fallback to raw timing on supported boards
In case of empty SPD or checksum error, fallback to raw timing on
supported boards.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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| d2246549 | 26-May-2011 |
York Sun <yorksun@freescale.com> |
powerpc/mpc8xxx: check SPD length before using part number
Only use DDR DIMM part number if SPD has valid length, to prevent from
display garbage in case SPD doesn't cover these fields.
Signed-off-
powerpc/mpc8xxx: check SPD length before using part number
Only use DDR DIMM part number if SPD has valid length, to prevent from
display garbage in case SPD doesn't cover these fields.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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| e090aa7c | 26-May-2011 |
York Sun <yorksun@freescale.com> |
powerpc/mpc8xxx: adjust DDR burst length and chop accroding to sdram width
If the bus width is 32-bit, burst chop should be disabled and burst length
should be 8. Read from SPD or other source to de
powerpc/mpc8xxx: adjust DDR burst length and chop accroding to sdram width
If the bus width is 32-bit, burst chop should be disabled and burst length
should be 8. Read from SPD or other source to determine the width.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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| 526cbff2 | 15-Apr-2011 |
Mingkai Hu <Mingkai.hu@freescale.com> |
powerpc/p2040: Add various p2040 specific information
Add P2040 SoC specific information:
* LIODN setup
* Portal configuration
* etc
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-
powerpc/p2040: Add various p2040 specific information
Add P2040 SoC specific information:
* LIODN setup
* Portal configuration
* etc
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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| 9829feff | 20-May-2011 |
Kumar Gala <galak@kernel.crashing.org> |
powerpc/85xx: Fix compile errors if CONFIG_SYS_{BR,OR}0_PRELIM aren't set
Add ifdef protection in LBC code to handle the case in which
CONFIG_SYS_BR0_PRELIM and CONFIG_SYS_OR0_PRELIM arent defined f
powerpc/85xx: Fix compile errors if CONFIG_SYS_{BR,OR}0_PRELIM aren't set
Add ifdef protection in LBC code to handle the case in which
CONFIG_SYS_BR0_PRELIM and CONFIG_SYS_OR0_PRELIM arent defined for a
build.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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| 03c0a924 | 14-Apr-2011 |
Andre Schwarz <andre.schwarz@matrix-vision.de> |
MPC83xx: add config options for memory setup.
CPO value and driver strength settings are board specifc.
Also allow SPD data fetch from any accessible I2C EEPROM.
Signed-off-by: Andre Schwarz <andre
MPC83xx: add config options for memory setup.
CPO value and driver strength settings are board specifc.
Also allow SPD data fetch from any accessible I2C EEPROM.
Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de>
Acked-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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| d49f8e04 | 05-May-2011 |
York Sun <yorksun@freescale.com> |
powerpc/mpc8xxx: reword max tCKmin message
Reword "The DIMM max tCKmin is ..." to "The DDR clock is faster than the slowest
DIMM(s) can support". Fixed interger type in printf as well.
Signed-off-b
powerpc/mpc8xxx: reword max tCKmin message
Reword "The DIMM max tCKmin is ..." to "The DDR clock is faster than the slowest
DIMM(s) can support". Fixed interger type in printf as well.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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